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ShubhamWaingade2024/README.md

💫 About Me:

Turning digital logic into real-world hardware. Passionate about RTL Design & Verification, Physical Design, and Embedded Systems. I enjoy designing processors, building hardware projects, and exploring computer architecture, automation, and emerging semiconductor technologies. Always learning, always building, and driven to solve engineering challenges through innovation.

🌐 Socials:

Discord LinkedIn email

💻 Tech Stack:

C C++ Java LaTeX JavaScript Perl Python Windows Terminal FastAPI Streamlit MongoDB MySQL Canva Figma Matplotlib NumPy Pandas scikit-learn GitHub Git Raspberry Pi

📊 GitHub Stats:



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  1. AXI-Memory-Verification AXI-Memory-Verification Public

    Developed a SystemVerilog-based verification environment for an AXI memory module featuring directed and constrained-random testcases, self-checking testbench components, and protocol compliance va…

    Verilog 1

  2. Floor-Cleaning-Bot Floor-Cleaning-Bot Public

    Compact autonomous cleaning robot integrating vacuum, sweeping, and liquid mopping. Features obstacle detection, efficient hardware integration, and CAD-optimized design. Built by a multidisciplina…

    C 1

  3. guardian_vision guardian_vision Public

    Guardian Vision is an AI-based safety monitoring system that detects falls or accidents using computer vision. The system sends instant alerts with location data, improving emergency response and d…

    Python 1

  4. KiCad-USB_to_UART KiCad-USB_to_UART Public

    Designed and implemented a USB-to-UART hardware interface using KiCad. Completed schematic, PCB layout, and routing while learning serial protocols and hardware design practices essential for embed…

    1

  5. Single_Cycle_32-Bit_RISC-V_Processor Single_Cycle_32-Bit_RISC-V_Processor Public

    A 32-bit single-cycle RISC-V processor designed in Verilog HDL. The project implements the processor datapath, control unit, ALU, register file, instruction memory, and data memory. Simulated using…

    Verilog 1

  6. UART UART Public

    UART Transmitter and Receiver implemented in Verilog HDL with functional verification using ModelSim

    Verilog 1