v3.0.7

What's Changed

• boot/rom: read chip ROM via clk toggling, with address-mode fallback by @urish in #53

Full Changelog: v3.0.6...v3.0.7

v3.0.6

What's Changed

• platform/rp2350: Fix bit masking logic by @smunaut in #52

New Contributors

• @smunaut made their first contribution in #52

Full Changelog: v3.0.5...v3.0.6

v3.0.5

What's Changed

• Dev release naming and factory test messages by @psychogenic in #51

Full Changelog: v3.0.4...v3.0.5

v3.0.4

What's Changed

• standardized version/version names by @psychogenic in #50

Full Changelog: v3.0.2...v3.0.4

v3.0.2

What's Changed

• Better, unified, factory test by @psychogenic in #49

Full Changelog: v3.0.1...v3.0.2

v3.0.1

What's Changed

• FPGA mux enhancements by @psychogenic in #48

Full Changelog: v3.0.0...v3.0.1

v3.0.0

What's Changed

• Action to build RP2350 UF2 by @psychogenic in #37
• Using actual factory test built by @psychogenic in #38
• VERSION file generation by @psychogenic in #39
• Updated docs by @psychogenic in #40
• Clean-up for ETR/RP2350 only support moving forward by @psychogenic in #41
• Support for easy serial-con file transfers by @psychogenic in #42
• Correct platform clock writer to SET/CLR GPIO_OUT by @pgfarley in #43
• New shuttles, revision tracking, minor tweaks by @psychogenic in #44
• Allow shuttle overrides for FPGA breakout by @psychogenic in #45
• Assign a GPIO map even if we do not have a breakout board installed by @psychogenic in #46

New Contributors

• @pgfarley made their first contribution in #43

Full Changelog: v2.0.4...v3.0.0

v2.0.4

What's Changed

• Make clock frequencies over 66.5MHz possible by @MichaelBell in #26
• Test with Wokwi on every commit by @urish in #29

New Contributors

• @urish made their first contribution in #29

Full Changelog: v2.0.3...v2.0.4

v2.0.3

Full Changelog: v2.0.2...v2.0.3

v2.0.2

Full Changelog: v2.0.1...v2.0.2