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@chedahub chedahub commented Oct 22, 2025

Description

This PR updates the Intermediate Language (IL) generation for the e_addi and e_add16i instructions on the PowerPC VLE architecture to ensure correct data-flow analysis.

Motivation and Context

For e_addi and e_add16i instructions, the IL was incorrectly interpreting the r0 register as a constant 0 instead of a register source. This was caused by the OTI_GPR0_ZERO flag.

Changes Made

The OTI_GPR0_ZERO flag has been removed.
As a result, r0 is now correctly treated as a general-purpose register in the IL, enabling accurate data-flow analysis.

  • Before: operToIL(il, oper1, OTI_GPR0_ZERO, ...)
  • After: operToIL(il, oper1)

This ensures that r0 is consistently treated as a register operand in the IL for these instruction.

Visual Comparison

  • Before
image image
  • After
image

@chedahub chedahub changed the title Fix(ppc/il): Treat r0 as a register in e_addi/e_add16i IL [PPC-VLE] Fix(ppc/il): Treat r0 as a register in e_addi/e_add16i IL Oct 28, 2025
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