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nickrallisonnickrallison
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CMake: Fix Configure Errors with Generated Files
1 parent e88a1fc commit 782b1f3

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2 files changed

+56
-41
lines changed

2 files changed

+56
-41
lines changed

‎passes/pmgen/CMakeLists.txt‎

Lines changed: 27 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,19 @@
11
add_library(yosys_passes_pmgen INTERFACE)
22

3-
function(pmgen_command _name _path)
3+
set(PMGEN_TARGETS "")
4+
5+
function(pmgen_command _name _path)
6+
set(GENERATED_HEADER ${yosys_BINARY_DIR}/${_path}/${_name}_pm.h)
7+
set(CUSTOM_TARGET_NAME ${_name}_pm_gen)
8+
49
add_custom_command(
5-
OUTPUT ${yosys_BINARY_DIR}/${_path}/${_name}_pm.h
6-
COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py -o ${yosys_BINARY_DIR}/${_path}/${_name}_pm.h -p ${_name} ${yosys_SOURCE_DIR}/${_path}/${_name}.pmg
10+
OUTPUT ${GENERATED_HEADER}
11+
COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py -o ${GENERATED_HEADER} -p ${_name} ${yosys_SOURCE_DIR}/${_path}/${_name}.pmg
712
DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py ${yosys_SOURCE_DIR}/${_path}/${_name}.pmg
813
COMMENT "Generating ${_path}/${_name}_pm.h..."
914
)
15+
add_custom_target(${CUSTOM_TARGET_NAME} DEPENDS ${GENERATED_HEADER})
16+
list(APPEND PMGEN_TARGETS ${CUSTOM_TARGET_NAME})
1017
endfunction()
1118

1219
pmgen_command(test_pmgen passes/pmgen)
@@ -21,9 +28,10 @@ pmgen_command(microchip_dsp_CREG techlibs/microchip)
2128
pmgen_command(microchip_dsp_cascade techlibs/microchip)
2229
pmgen_command(xilinx_srl techlibs/xilinx)
2330

31+
set(PEEPOPT_HEADER ${yosys_BINARY_DIR}/passes/opt/peepopt_pm.h)
2432
add_custom_command(
25-
OUTPUT ${yosys_BINARY_DIR}/passes/opt/peepopt_pm.h
26-
COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py -o ${yosys_BINARY_DIR}/passes/opt/peepopt_pm.h -p peepopt
33+
OUTPUT ${PEEPOPT_HEADER}
34+
COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py -o ${PEEPOPT_HEADER} -p peepopt
2735
${yosys_SOURCE_DIR}/passes/opt/peepopt_shiftmul_right.pmg
2836
${yosys_SOURCE_DIR}/passes/opt/peepopt_shiftmul_left.pmg
2937
${yosys_SOURCE_DIR}/passes/opt/peepopt_shiftadd.pmg
@@ -39,9 +47,13 @@ add_custom_command(
3947
${yosys_SOURCE_DIR}/passes/opt/peepopt_formal_clockgateff.pmg
4048
COMMENT "Generating passes/pmgen/peepopt_pm.h..."
4149
)
50+
add_custom_target(peepopt_pm_gen DEPENDS ${PEEPOPT_HEADER})
51+
list(APPEND PMGEN_TARGETS peepopt_pm_gen)
52+
53+
4254

4355
target_sources(yosys_passes_pmgen INTERFACE
44-
test_pmgen.cc
56+
${CMAKE_CURRENT_SOURCE_DIR}/test_pmgen.cc
4557
${yosys_SOURCE_DIR}/techlibs/ice40/ice40_dsp.cc
4658
${yosys_SOURCE_DIR}/techlibs/ice40/ice40_wrapcarry.cc
4759
${yosys_SOURCE_DIR}/techlibs/xilinx/xilinx_dsp.cc
@@ -50,22 +62,13 @@ target_sources(yosys_passes_pmgen INTERFACE
5062
${yosys_SOURCE_DIR}/techlibs/xilinx/xilinx_srl.cc
5163
)
5264

53-
target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/passes/pmgen/test_pmgen_pm.h)
54-
55-
target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/ice40/ice40_dsp_pm.h)
56-
target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/ice40/ice40_wrapcarry_pm.h)
57-
58-
target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/xilinx/xilinx_dsp_pm.h)
59-
target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/xilinx/xilinx_dsp48a_pm.h)
60-
target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/xilinx/xilinx_dsp_CREG_pm.h)
61-
target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/xilinx/xilinx_dsp_cascade_pm.h)
62-
63-
target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/microchip/microchip_dsp_pm.h)
64-
target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/microchip/microchip_dsp_CREG_pm.h)
65-
target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/microchip/microchip_dsp_cascade_pm.h)
66-
67-
target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/passes/opt/peepopt_pm.h)
68-
69-
target_sources(yosys_passes_pmgen PUBLIC ${yosys_BINARY_DIR}/techlibs/xilinx/xilinx_srl_pm.h)
65+
target_include_directories(yosys_passes_pmgen INTERFACE
66+
${yosys_BINARY_DIR}/passes/pmgen
67+
${yosys_BINARY_DIR}/techlibs/ice40
68+
${yosys_BINARY_DIR}/techlibs/xilinx
69+
${yosys_BINARY_DIR}/techlibs/microchip
70+
${yosys_BINARY_DIR}/passes/opt
71+
)
7072

71-
target_link_libraries(yosys PUBLIC yosys_passes_pmgen)
73+
add_dependencies(yosys_passes_pmgen ${PMGEN_TARGETS})
74+
target_link_libraries(yosys PUBLIC yosys_passes_pmgen)

‎techlibs/quicklogic/CMakeLists.txt‎

Lines changed: 29 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,36 @@
11
add_library(yosys_techlibs_quicklogic INTERFACE)
22

3-
function(pmgen_command _name)
3+
set(QUICKLOGIC_GEN_TARGETS "")
4+
5+
function(pmgen_command _name)
6+
set(GENERATED_HEADER ${CMAKE_CURRENT_BINARY_DIR}/${_name}_pm.h)
7+
set(CUSTOM_TARGET_NAME ${_name}_pm_gen)
8+
49
add_custom_command(
5-
OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${_name}_pm.h
6-
COMMAND ${Python3_EXECUTABLE} ${yosys_SOURCE_DIR}/passes/pmgen/pmgen.py -o ${CMAKE_CURRENT_BINARY_DIR}/${_name}_pm.h -p ${_name} ${CMAKE_CURRENT_SOURCE_DIR}/${_name}.pmg
10+
OUTPUT ${GENERATED_HEADER}
11+
COMMAND ${Python3_EXECUTABLE} ${yosys_SOURCE_DIR}/passes/pmgen/pmgen.py -o ${GENERATED_HEADER} -p ${_name} ${CMAKE_CURRENT_SOURCE_DIR}/${_name}.pmg
712
DEPENDS ${yosys_SOURCE_DIR}/passes/pmgen/pmgen.py ${CMAKE_CURRENT_SOURCE_DIR}/${_name}.pmg
8-
COMMENT "Generating passes/pmgen/${_name}_pm.h..."
13+
COMMENT "Generating techlibs/quicklogic/${_name}_pm.h..."
914
)
15+
16+
add_custom_target(${CUSTOM_TARGET_NAME} DEPENDS ${GENERATED_HEADER})
17+
list(APPEND QUICKLOGIC_GEN_TARGETS ${CUSTOM_TARGET_NAME})
1018
endfunction()
1119

1220
pmgen_command(ql_dsp_macc)
1321

22+
set(BRAM_SIM_V_FILE ${CMAKE_CURRENT_BINARY_DIR}/qlf_k6n10f/bram_types_sim.v)
23+
add_custom_command(
24+
OUTPUT ${BRAM_SIM_V_FILE}
25+
COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/qlf_k6n10f
26+
COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/qlf_k6n10f/generate_bram_types_sim.py ${BRAM_SIM_V_FILE}
27+
DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/qlf_k6n10f/generate_bram_types_sim.py
28+
COMMENT "Generating techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v..."
29+
)
30+
31+
add_custom_target(bram_types_sim_v_gen DEPENDS ${BRAM_SIM_V_FILE})
32+
list(APPEND QUICKLOGIC_GEN_TARGETS bram_types_sim_v_gen)
33+
1434
target_sources(yosys_techlibs_quicklogic INTERFACE
1535
synth_quicklogic.cc
1636
ql_bram_merge.cc
@@ -21,18 +41,11 @@ target_sources(yosys_techlibs_quicklogic INTERFACE
2141
ql_ioff.cc
2242
)
2343

24-
add_custom_command(
25-
COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/qlf_k6n10f
26-
COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/qlf_k6n10f/generate_bram_types_sim.py ${CMAKE_CURRENT_BINARY_DIR}/qlf_k6n10f/bram_types_sim.v
27-
DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/qlf_k6n10f/generate_bram_types_sim.py
28-
OUTPUT qlf_k6n10f/bram_types_sim.v
29-
COMMENT "Generating techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v..."
44+
target_include_directories(yosys_techlibs_quicklogic INTERFACE
45+
${CMAKE_CURRENT_BINARY_DIR}
3046
)
3147

32-
target_sources(yosys_techlibs_quicklogic PUBLIC
33-
${CMAKE_CURRENT_BINARY_DIR}/ql_dsp_macc_pm.h
34-
${CMAKE_CURRENT_BINARY_DIR}/qlf_k6n10f/bram_types_sim.v
35-
)
48+
add_dependencies(yosys_techlibs_quicklogic ${QUICKLOGIC_GEN_TARGETS})
3649

3750
target_link_libraries(yosys PUBLIC yosys_techlibs_quicklogic)
3851

@@ -50,13 +63,12 @@ add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/libmap_brams.txt")
5063
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/libmap_brams_map.v")
5164
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/brams_map.v")
5265
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/brams_sim.v")
53-
add_gen_share_file("share/quicklogic/qlf_k6n10f" "${CMAKE_CURRENT_BINARY_DIR}/qlf_k6n10f/bram_types_sim.v")
66+
add_gen_share_file("share/quicklogic/qlf_k6n10f" "${BRAM_SIM_V_FILE}")
5467
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/cells_sim.v")
5568
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/ffs_map.v")
5669
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/dsp_sim.v")
5770
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/dsp_map.v")
5871
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/dsp_final_map.v")
5972
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/TDP18K_FIFO.v")
6073
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/ufifo_ctl.v")
61-
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/sram1024x18_mem.v")
62-
74+
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/sram1024x18_mem.v")

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