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Accept (and ignore) SystemVerilog unique/priority if.
#5141
opened May 23, 2025 by
garytwong
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ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
#5135
opened May 21, 2025 by
widlarizer
•
Draft
6 tasks
Add association-list-based helper functions into Rosette backend
#5128
opened May 17, 2025 by
gussmith23
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2 tasks
Disable STRIP operations when appropriate.
merge-after-jf
Merge: PR will be merged after the next Dev JF unless concerns are raised
#5127
opened May 17, 2025 by
RonxBulld
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Add state_dependent_path_declaration so that
ifnone
can be parsed
#5121
opened May 14, 2025 by
FlinkbaumFAU
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check: promote some problems to errors by default, add -permissive
#5058
opened Apr 23, 2025 by
widlarizer
•
Draft
techlibs/lattice: add missing clock muxes to ECP5 block ram blackboxes
#5045
opened Apr 21, 2025 by
danderson
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opt_clean: handle undriven and x-bit driven bits consistently
#5004
opened Apr 8, 2025 by
widlarizer
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techmap: map $alu to $fa instead of relying on extract_fa
enhancement
#4997
opened Apr 7, 2025 by
widlarizer
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1 task
Derive abstract cells in top module during hierarchy
#4930
opened Mar 6, 2025 by
KrystalDelusion
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Draft
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