Update ElemRV-H and ElemRV-C: flash programming, reset handling, and floorplan rework - #27
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Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
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Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Since we support two floorplan modes now (relaxed and tapeout), Claude should be aware of both and should have new target densities for each. Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
This namespace can flash a SPI flash via JTAG or flashrom (busbirate). It also uses smaller image sizes for JTAG and truncates the image to fit the SPI flash via flashrom. Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
The total flash size is defined with 512kB in Zephyr. Generate images which fit this image size and truncate them later in case larger images are required. Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
This variable allows to switch between a relaxed and tape-out floorplan. Relaxed increases the layout size and therefore improves the layouttime, while tape-out is more accurate. Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Address all recent changes in the documentation to reflect the current tooling. Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Make sure ElemRV-N still compiles without properly connect the SPI reset signal. ElemRV-N will be updated next. Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
* Decrease general-purpose pins from 12 to 11 * Add SPI reset pin to reset the ext. SPI flash * Add reset domain to release SPI reset before CPU reset * Switch both 4kB SRAM macros against a single 8kB one * Increase debug clock domain to mach system * Add relaxed floorplan Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
* Decrease general-purpose pins from 12 to 11 * Add SPI reset pin to reset the ext. SPI flash * Add reset domain to release SPI reset before CPU reset * Switch both 4kB SRAM macros against a single 8kB one * Place i-cache as memory (tag and data) * Increase debug clock domain to mach system * Add relaxed floorplan Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
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Fixes c2aeb36 which removed the revision for VexiiRiscv. Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Those files define versions and CI is pulling newer version, which might introduce compile issues. Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
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This PR prepares ElemRV-H and ElemRV-C for the SG13CMOS5L tape-out and reworks
how the SPI flash is programmed and reset.
Flash programming
(flashrom, pads the image to chip size on demand) and flash:jtag (OpenOCD
via the new SPI XIP flash write support in Nafarr/Zibal).
both zephyr:compile and baremetal:compile maintain the image_container.img
symlink the flash tasks consume.
Reset handling
platforms, driven by a dedicated "flash" reset domain that releases ~40 us
before the CPU so the flash finishes reset recovery before the first XIP
fetch. The flash also re-resets on ndmreset and ESM errors.
Floorplan
~60% utilization, fast and reliable iteration) and "tapeout" (~75-80%,
signoff). The generate step warns when running relaxed.
ElemRV-C I-cache data/tag macros at the west edge, following the learned
PDN constraints (no core-boundary abutment, row-aligned offsets, spacing
for per-macro power rings).
from measured post-repair design areas via the update-chip-size skill.
Infrastructure
iCacheTagRams accessor, OpenROADTools floorplan/ABC support, shared
VexiiRiscv OpenOCD configs).
FLOORPLAN variable.