projects/ad4052_ardz: fix and update

Fixes quartus scripts for ad4052 in quartus. Also adds optimization
options for timing closure of the project.
Removes wrong timing constraints for the coraz7s.

Signed-off-by: Carlos Souza <[email protected]>

Author: caosjr

projects/ad4052_ardz/common/ad4052_qsys.tcl

@@ -139,6 +139,7 @@ add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset
 add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd
 add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi
 add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data
+add_connection spi_engine_interconnect_0.m_offload_active_ctrl spi_engine_execution_0.s_offload_active_ctrl
 add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync
 
 add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd

projects/ad4052_ardz/coraz7s/system_constr.xdc

@@ -15,9 +15,3 @@ set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33}          [get_ports adc
 # rename auto-generated clock for SPIEngine to spi_clk - 160MHz
 # NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk
 create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]
-
-# relax the SDO path to help closing timing at high frequencies
-set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
-set_multicycle_path -hold  7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
-set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/spi_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
-set_multicycle_path -hold  7 -to [get_cells -hierarchical -filter {NAME=~*/spi_adc_execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]

projects/ad4052_ardz/de10nano/system_project.tcl

@@ -39,6 +39,8 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_cnv
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_gp0
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_gp1
 
+#ad4052 requires both options for closing time
+set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
 set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
 
 execute_flow -compile