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Doc filter #192
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f1e88cc
infrastructure refactorization
IstvanZsSzekely e0e4835
infrastructure refactorization: Fixes
IstvanZsSzekely 836fbe3
infrastructure refactorization: Refactoring
IstvanZsSzekely c99cfd7
infrastructure refactorization: Generalized scoreboard
IstvanZsSzekely a463503
infrastructure refactorization: Updated DMA loopback project
IstvanZsSzekely fb7eadf
infrastructure refactorization: Fixed address value in DMA loopback f…
IstvanZsSzekely 5ee6bb3
infrastructure refactorization: Updated IP level testbenches
IstvanZsSzekely 29b8873
infrastructure refactorization: IP level updates
IstvanZsSzekely 53c1327
infrastructure refactorization: Updated Project level testbenches
IstvanZsSzekely d2aa755
infrastructure refactorization: Updates and fixes
IstvanZsSzekely 1670e8e
ad7616: Fixes
IstvanZsSzekely 269401b
dma_flock: Fixed testbench after rebase
IstvanZsSzekely 41dfa6f
adi_datatypes: Added FIFO and LIFO class implementation
IstvanZsSzekely 2991e44
infrastructure refactorization: Minor fixes
IstvanZsSzekely 1fe651d
util_axis_fifo_asym: Initial testbench commit
IstvanZsSzekely fc60809
util_axis_fifo_asym: Updated after rebase
IstvanZsSzekely 2693a75
util_axis_fifo_asym: Updates and fixes
IstvanZsSzekely 98691b5
util_axis_fifo_asym: Updated waveform configuration
IstvanZsSzekely 2f11dc9
util_axis_fifo: Initial testbench commit
IstvanZsSzekely 76665e5
util_axis_fifo: Updated ADI AXI and AXIS agents
IstvanZsSzekely 30018ba
util_axis_fifo: Fixed ADI AXI agent run call
IstvanZsSzekely 8ee0dee
General updates:
IstvanZsSzekely a5337ee
SPI VIP update
IstvanZsSzekely a888f41
General updates: Updated VIP clocking and reset calls
IstvanZsSzekely 46b53bb
general: Change while(1) calls to forever
IstvanZsSzekely afcd1be
ADI AMD agent abstractization
IstvanZsSzekely e87f281
ADI AMD agent abstractization: Added linker macro to simplify VIP lin…
IstvanZsSzekely a6483d7
ADI AMD agent abstractication: Updated testbenches for the base envir…
IstvanZsSzekely a8c9d2d
library/vip/amd/axi/s_axi_sequencer: Added memory access functions
IstvanZsSzekely bf9ae58
library/vip/amd/axi/s_axi_sequencer: Cosmetic change
IstvanZsSzekely 85d89c1
library/vip/amd: Updated ADI agent function calls to fix a null-objec…
IstvanZsSzekely 13863e7
scoreboard: Simplified to AXIS datastream verification
IstvanZsSzekely 1961396
scoreboard: Commented test program
IstvanZsSzekely bffecca
packet_filter: Initial commit
IstvanZsSzekely baf31fd
packet_filter: Add dependencies
IstvanZsSzekely a878252
packet_filter: Add sandbox testbench
IstvanZsSzekely 4a78d66
docs: Packet filter testbench
IstvanZsSzekely c47ddf7
docs/testbenches/ip/packet_filter: PR requests
IstvanZsSzekely fe43db1
docs/testbenches/ip/packet_filter: Fix typo
IstvanZsSzekely File filter
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|---|---|---|
| @@ -0,0 +1,192 @@ | ||
| .. _packet_filter: | ||
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| Packet filter | ||
| ================================================================================ | ||
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| Overview | ||
| ------------------------------------------------------------------------------- | ||
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| The purpose of this testbench is to give engineers a sandbox testbench, where | ||
| they can check out how to implement and use a filter. | ||
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| Block design | ||
| ------------------------------------------------------------------------------- | ||
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| The block design is based on the test harness with the addition of two AXI4 | ||
| Stream VIPs from AMD. This testbench does not require the presence of the test | ||
| harness, as it can work without it, but since it was created based on the base | ||
| design, this was inherited. One of the VIPs is configured as master, while the | ||
| other one is configured as slave. The TREADY, TLAST and TKEEP signals are set to | ||
| be enabled for the VIPs. | ||
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| Block diagram | ||
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
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| .. image:: ../axis_sequencers/axis_sequencers_tb.svg | ||
| :width: 800 | ||
| :align: center | ||
| :alt: Scoreboard/Testbench block diagram | ||
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| Configuration parameters and modes | ||
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
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| There are no parameters that can be configured in the testbench configuration | ||
| files. | ||
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| Build parameters | ||
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
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| There are no build parameters for this testbench. | ||
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| Configuration files | ||
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
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| As this is a sandbox testbench, engineers are encouraged to change parameters | ||
| and see what happens in the simulation. Since there are no parameters available | ||
| for edit, the coniguration file's purpose is to give the testbench instance a | ||
| name. | ||
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| Tests | ||
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
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| The following test program file is available: | ||
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| ============ ============================== | ||
| Test program Usage | ||
| ============ ============================== | ||
| test_program Creates a basic test stimulus. | ||
| ============ ============================== | ||
|
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| Available configurations & tests combinations | ||
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | ||
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| The test program is compatible with the configuration. | ||
|
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| Test stimulus | ||
| ------------------------------------------------------------------------------- | ||
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| The test program is responsible for configuring and running the sequencers, | ||
| while checking the data with a scoreboard. A filter class is implemented that is | ||
| used to filter data. | ||
|
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| Environment Bringup | ||
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
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| The steps of the environment bringup are: | ||
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| * Create the environment | ||
| * Start the environment | ||
| * Start the clocks | ||
| * Assert the resets | ||
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| Packet filtering testing | ||
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
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| * Filter class are implemented which is a simple data filter | ||
| * Before the resets are asserted, the filter is instantiated | ||
| * The filter is connected with the publisher filters | ||
| * The master and slave sequencers are configured and then the resets are | ||
| asserted | ||
| * The scoreboard is subscribed to the master and slave sequencers' publisher | ||
| * The scoreboard is started | ||
| * The sequencers are started | ||
| * Scoreboard waits until the verification is complete | ||
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| .. warning:: | ||
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| Depending on the packet size and amount, the simulation may end before all of | ||
| the data is verified, which may cause runtime errors! | ||
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| Building the test bench | ||
| ------------------------------------------------------------------------------- | ||
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| The testbench is built upon ADI's generic HDL reference design framework. | ||
| ADI does not distribute compiled files of these projects so they must be built | ||
| from the sources available :git-hdl:`here </>` and :git-testbenches:`here </>`, | ||
| with the specified hierarchy described :ref:`build_tb set_up_tb_repo`. | ||
| To get the source you must | ||
| `clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__ | ||
| the HDL repository, and then build the project as follows: | ||
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| **Linux/Cygwin/WSL** | ||
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| *Example 1* | ||
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| Building and simulating the testbench using only the command line. | ||
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| .. shell:: | ||
| :showuser: | ||
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| $cd testbenches/ip/packet_filter | ||
| $make | ||
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| *Example 2* | ||
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| Building and simulating the testbench using the Vivado GUI. This command will | ||
| launch Vivado, will run the simulation and display the waveforms. | ||
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| .. shell:: | ||
| :showuser: | ||
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| $cd testbenches/ip/packet_filter | ||
| $make MODE=gui | ||
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| *Example 3* | ||
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| Build a particular combination of test and configuration, using the Vivado GUI. | ||
| This command will launch Vivado, will run the simulation and display the | ||
| waveforms. | ||
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| .. shell:: | ||
| :showuser: | ||
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| $cd testbenches/ip/packet_filter | ||
| $make MODE=gui CFG=cfg1 TST=test_program | ||
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| The built project can be found in the ``runs`` folder, where each configuration | ||
| specific build has its own folder named after the configuration file's name. | ||
| Example: if the following command was run for a single configuration in the | ||
| clean folder (no runs folder available): | ||
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| ``make CFG=cfg1`` | ||
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| Then the subfolder under ``runs`` name will be: | ||
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| ``cfg1`` | ||
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| Resources | ||
| ------------------------------------------------------------------------------- | ||
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| Testbenches related dependencies | ||
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
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| .. include:: ../../common/dependency_common.rst | ||
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| Testbench specific dependencies: | ||
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| .. list-table:: | ||
| :widths: 30 45 25 | ||
| :header-rows: 1 | ||
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| * - SV dependency name | ||
| - Source code link | ||
| - Documentation link | ||
| * - FILTER | ||
| - :git-testbenches:`library/utilities/filter_pkg.sv` | ||
| - --- | ||
| * - M_AXIS_SEQUENCER | ||
| - :git-testbenches:`library/vip/amd/m_axis_sequencer.sv` | ||
| - --- | ||
| * - PUBLISHER-SUBSCRIBER | ||
| - :git-testbenches:`library/utilities/pub_sub_pkg.sv` | ||
| - --- | ||
| * - S_AXIS_SEQUENCER | ||
| - :git-testbenches:`library/vip/amd/s_axis_sequencer.sv` | ||
| - --- | ||
| * - SCOREBOARD | ||
| - :git-testbenches:`library/drivers/common/scoreboard.sv` | ||
| - --- | ||
|
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| .. include:: ../../../common/more_information.rst | ||
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| .. include:: ../../../common/support.rst | ||
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