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testbenches/ip/spi_engine: Upgrade spi_engine testbench for SDO extension #240

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70e0b21
library/vip/spi_vip: update to n lanes
caosjr Jun 23, 2025
4de3a2f
library/drivers/spi_engine: update to support n lanes
caosjr Jun 23, 2025
575f0e6
library/regmaps/adi_regmap_spi_engine_pkg.sv: update major version
caosjr Jun 23, 2025
097617e
testbenches/ip/spi_engine: update to support n lanes
caosjr Jun 23, 2025
2061f93
docs/testbenches/project_based: Updated to NUM_OF_SDIO parameter
caosjr Aug 6, 2025
398f953
testbenches/project/ad738x: Update testbench
caosjr Aug 15, 2025
e791a3c
testbenches/ip/spi_engine: update test_lanes
caosjr Aug 16, 2025
bcd4b55
testbenches/ip/spi_engine: fix test_lanes
caosjr Sep 1, 2025
4e21838
testbenches/ip/spi_engine: update test_program and test_slowdata
caosjr Sep 3, 2025
9de5afa
library/regmaps: update spi engine version
caosjr Sep 23, 2025
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50 changes: 25 additions & 25 deletions docs/testbenches/project_based/ad463x/index.rst
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Expand Up @@ -35,7 +35,7 @@ The following parameters of this project that can be configured:

- CLK_MODE: defines clocking mode of the device's digital interface:
Options: 0 - SPI mode, 1 - Echo-clock or Master clock mode
- NUM_OF_SDI: defines the number of MOSI lines of the SPI interface:
- NUM_OF_SDIO: defines the number of MOSI lines of the SPI interface:
Options: 1 - Interleaved mode, 2 - 1 lane per channel,
4 - 2 lanes per channel, 8 - 4 lanes per channel
- CAPTURE_ZONE: defines the capture zone of the next sample.
Expand All @@ -54,30 +54,30 @@ The following configuration files are available:
+-----------------------+-----------------------------------------------+
| Configuration mode | Parameters |
| +----------+------------+--------------+--------+
| | CLK_MODE | NUM_OF_SDI | CAPTURE_ZONE | DDR_EN |
+=======================+==========+============+==============+========+
| cfg_cm0_sdi2_cz1_ddr0 | 0 | 2 | 1 | 0 |
+-----------------------+----------+------------+--------------+--------+
| cfg_cm0_sdi2_cz2_ddr0 | 0 | 2 | 2 | 0 |
+-----------------------+----------+------------+--------------+--------+
| cfg_cm0_sdi4_cz2_ddr0 | 0 | 4 | 2 | 0 |
+-----------------------+----------+------------+--------------+--------+
| cfg_cm0_sdi8_cz2_ddr0 | 0 | 8 | 2 | 0 |
+-----------------------+----------+------------+--------------+--------+
| cfg_cm1_sdi1_cz2_ddr0 | 1 | 1 | 2 | 0 |
+-----------------------+----------+------------+--------------+--------+
| cfg_cm1_sdi2_cz2_ddr0 | 1 | 2 | 2 | 0 |
+-----------------------+----------+------------+--------------+--------+
| cfg_cm1_sdi2_cz2_ddr1 | 1 | 2 | 2 | 1 |
+-----------------------+----------+------------+--------------+--------+
| cfg_cm1_sdi4_cz2_ddr0 | 1 | 4 | 2 | 0 |
+-----------------------+----------+------------+--------------+--------+
| cfg_cm1_sdi4_cz2_ddr1 | 1 | 4 | 2 | 1 |
+-----------------------+----------+------------+--------------+--------+
| cfg_cm1_sdi8_cz2_ddr0 | 1 | 8 | 2 | 0 |
+-----------------------+----------+------------+--------------+--------+
| cfg_cm1_sdi8_cz2_ddr1 | 1 | 8 | 2 | 1 |
+-----------------------+----------+------------+--------------+--------+
| | CLK_MODE | NUM_OF_SDIO | CAPTURE_ZONE | DDR_EN |
+=======================+==========+=============+==============+========+
| cfg_cm0_sdi2_cz1_ddr0 | 0 | 2 | 1 | 0 |
+-----------------------+----------+-------------+--------------+--------+
| cfg_cm0_sdi2_cz2_ddr0 | 0 | 2 | 2 | 0 |
+-----------------------+----------+-------------+--------------+--------+
| cfg_cm0_sdi4_cz2_ddr0 | 0 | 4 | 2 | 0 |
+-----------------------+----------+-------------+--------------+--------+
| cfg_cm0_sdi8_cz2_ddr0 | 0 | 8 | 2 | 0 |
+-----------------------+----------+-------------+--------------+--------+
| cfg_cm1_sdi1_cz2_ddr0 | 1 | 1 | 2 | 0 |
+-----------------------+----------+-------------+--------------+--------+
| cfg_cm1_sdi2_cz2_ddr0 | 1 | 2 | 2 | 0 |
+-----------------------+----------+-------------+--------------+--------+
| cfg_cm1_sdi2_cz2_ddr1 | 1 | 2 | 2 | 1 |
+-----------------------+----------+-------------+--------------+--------+
| cfg_cm1_sdi4_cz2_ddr0 | 1 | 4 | 2 | 0 |
+-----------------------+----------+-------------+--------------+--------+
| cfg_cm1_sdi4_cz2_ddr1 | 1 | 4 | 2 | 1 |
+-----------------------+----------+-------------+--------------+--------+
| cfg_cm1_sdi8_cz2_ddr0 | 1 | 8 | 2 | 0 |
+-----------------------+----------+-------------+--------------+--------+
| cfg_cm1_sdi8_cz2_ddr1 | 1 | 8 | 2 | 1 |
+-----------------------+----------+-------------+--------------+--------+

Tests
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Expand Down
16 changes: 8 additions & 8 deletions docs/testbenches/project_based/ad738x/index.rst
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Expand Up @@ -36,7 +36,7 @@ The following parameters of this project that can be configured:
- ALERT_SPI_N: defines if a known pin will operate as a serial data output pin
or alert indication pin:
Options: 0 - Serial Data Output Pin, 1 - Alert Indication Ouput Pin
- NUM_OF_SDI: defines the number of MOSI lines of the SPI interface:
- NUM_OF_SDIO: defines the number of MOSI lines of the SPI interface:
Options: 1 - Interleaved mode, 2 - 1 lane per channel,
4 - 2 lanes per channel

Expand All @@ -45,13 +45,13 @@ Configuration files

The following configuration files are available:

+-----------------------+--------------------------+
| Configuration mode | Parameters |
| +----------+---------------+
| | ALERT_SPI_N | NUM_OF_SDI |
+=======================+=============+============+
| cfg1 | 0 | 2 |
+-----------------------+-------------+------------+
+-----------------------+---------------------------+
| Configuration mode | Parameters |
| +----------+----------------+
| | ALERT_SPI_N | NUM_OF_SDIO |
+=======================+=============+=============+
| cfg1 | 0 | 2 |
+-----------------------+-------------+-------------+

Tests
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Expand Down
20 changes: 10 additions & 10 deletions docs/testbenches/project_based/ad7606/index.rst
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Expand Up @@ -39,7 +39,7 @@ The following parameters of this project that can be configured:
Options: 0 - without external clock, 1 - with external clock
- INTF: defines the interface type:
Options: 0 - Parallel, 1 - Serial
- NUM_OF_SDI: defines the number of MOSI lines of the SPI interface:
- NUM_OF_SDIO: defines the number of MOSI lines of the SPI interface:
Options: 1 - Interleaved mode, 2 - 1 lane per channel,
4 - 2 lanes per channel, 8 - 4 lanes per channel

Expand All @@ -50,15 +50,15 @@ The following configuration files are available:

+-----------------------+------------------------------------------+
| Configuration mode | Parameters |
| +------------+---------+------+------------+
| | DEV_CONFIG | EXT_CLK | INTF | NUM_OF_SDI |
+=======================+============+=========+======+============+
| cfg1 | 0 | 0 | 0 | 1 |
+-----------------------+------------+---------+------+------------+
| cfg2 | 1 | 0 | 0 | 1 |
+-----------------------+------------+---------+------+------------+
| cfg3 | 2 | 0 | 0 | 1 |
+-----------------------+------------+---------+------+------------+
| +------------+---------+------+-------------+
| | DEV_CONFIG | EXT_CLK | INTF | NUM_OF_SDIO |
+=======================+============+=========+======+=============+
| cfg1 | 0 | 0 | 0 | 1 |
+-----------------------+------------+---------+------+-------------+
| cfg2 | 1 | 0 | 0 | 1 |
+-----------------------+------------+---------+------+-------------+
| cfg3 | 2 | 0 | 0 | 1 |
+-----------------------+------------+---------+------+-------------+

Tests
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Expand Down
4 changes: 2 additions & 2 deletions docs/testbenches/project_based/pulsar_adc/index.rst
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Expand Up @@ -33,7 +33,7 @@ The following parameters of this project that can be configured:

- CLK_MODE: defines clocking mode of the device's digital interface:
Options: 0 - SPI mode
- NUM_OF_SDI: defines the number of MOSI lines of the SPI interface:
- NUM_OF_SDIO: defines the number of MOSI lines of the SPI interface:
Options: 1 - Interleaved mode
- CAPTURE_ZONE: defines the capture zone of the next sample.
There are two capture zones: 1 - from negative edge of the BUSY line
Expand All @@ -50,7 +50,7 @@ The following configuration file is available:
+-----------------------+-----------------------------------------------+
| Configuration mode | Parameters |
| +----------+------------+--------------+--------+
| | CLK_MODE | NUM_OF_SDI | CAPTURE_ZONE | DDR_EN |
| | CLK_MODE |NUM_OF_SDIO | CAPTURE_ZONE | DDR_EN |
+=======================+==========+============+==============+========+
| cfg1 | 0 | 2 | 1 | 0 |
+-----------------------+----------+------------+--------------+--------+
Expand Down
6 changes: 3 additions & 3 deletions docs/testbenches/project_based/template/_index.rst
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Expand Up @@ -52,7 +52,7 @@ The following parameters of this project that can be configured:

- CLK_MODE: defines clocking mode of the device's digital interface:
Options: 0 - SPI mode, 1 - Echo-clock or Master clock mode
- NUM_OF_SDI: defines the number of MOSI lines of the SPI interface:
- NUM_OF_SDIO: defines the number of MOSI lines of the SPI interface:
Options: 1 - Interleaved mode, 2 - 1 lane per channel,
4 - 2 lanes per channel, 8 - 4 lanes per channel
- CAPTURE_ZONE: defines the capture zone of the next sample.
Expand All @@ -75,7 +75,7 @@ The following are available configurations for the testbench:
+-----------------------+-----------------------------------------------+
| Configuration mode | Parameters |
| +----------+------------+--------------+--------+
| | CLK_MODE | NUM_OF_SDI | CAPTURE_ZONE | DDR_EN |
| | CLK_MODE |NUM_OF_SDIO | CAPTURE_ZONE | DDR_EN |
+=======================+==========+============+==============+========+
| cfg_cm0_sdi2_cz1_ddr0 | 0 | 2 | 1 | 0 |
+-----------------------+----------+------------+--------------+--------+
Expand Down Expand Up @@ -112,7 +112,7 @@ The following are available configurations for the testbench:
-
* -
- CLK_MODE
- NUM_OF_SDI
- NUM_OF_SDIO
- CAPTURE_ZONE
- DDR_EN
* - cfg_cm0_sdi2_cz1_ddr0
Expand Down
20 changes: 13 additions & 7 deletions library/drivers/spi_engine/spi_engine_api_pkg.sv
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Expand Up @@ -86,17 +86,23 @@ package spi_engine_api_pkg;
this.axi_write(GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO_OFFLOAD0_CDM_FIFO(cmd));
endtask

task sdo_offload_fifo_write(input bit [31:0] data);
this.axi_write(GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO), `SET_AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO_OFFLOAD0_SDO_FIFO(data));
task sdo_offload_fifo_write(input bit [31:0] data[]);
foreach (data[i]) begin
this.axi_write(GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO), `SET_AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO_OFFLOAD0_SDO_FIFO(data[i]));
end
endtask

task sdo_fifo_write(input bit [31:0] data);
this.axi_write(GetAddrs(AXI_SPI_ENGINE_SDO_FIFO), `SET_AXI_SPI_ENGINE_SDO_FIFO_SDO_FIFO(data));
task sdo_fifo_write(input bit [31:0] data[]);
foreach (data[i]) begin
this.axi_write(GetAddrs(AXI_SPI_ENGINE_SDO_FIFO), `SET_AXI_SPI_ENGINE_SDO_FIFO_SDO_FIFO(data[i]));
end
endtask

task sdi_fifo_read(output logic [31:0] data);
this.axi_read(GetAddrs(AXI_SPI_ENGINE_SDI_FIFO), val);
data = `GET_AXI_SPI_ENGINE_SDI_FIFO_SDI_FIFO(val);
task sdi_fifo_read(ref logic [31:0] data[]);
foreach (data[i]) begin
this.axi_read(GetAddrs(AXI_SPI_ENGINE_SDI_FIFO), val);
data[i] = `GET_AXI_SPI_ENGINE_SDI_FIFO_SDI_FIFO(val);
end
endtask

task offload_mem_assert_reset();
Expand Down
12 changes: 8 additions & 4 deletions library/drivers/spi_engine/spi_engine_instr_pkg.sv
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Expand Up @@ -12,10 +12,14 @@ package spi_engine_instr_pkg;
`define INST_WRD (32'h0000_0300 | (`NUM_OF_WORDS-1))

// Configuration register instructions
`define INST_CFG (32'h0000_2100 | (`SDO_IDLE_STATE << 3) | (`THREE_WIRE << 2) | (`CPOL << 1) | `CPHA)
`define INST_PRESCALE (32'h0000_2000 | `CLOCK_DIVIDER)
`define INST_DLENGTH (32'h0000_2200 | `DATA_DLENGTH)
`define SET_DLENGTH(d) ((`INST_DLENGTH) & ~32'hFF | (d & 8'hFF))
`define INST_CFG (32'h0000_2100 | (`SDO_IDLE_STATE << 3) | (`THREE_WIRE << 2) | (`CPOL << 1) | `CPHA)
`define INST_PRESCALE (32'h0000_2000 | `CLOCK_DIVIDER)
`define INST_DLENGTH (32'h0000_2200 | `DATA_DLENGTH)
`define SET_DLENGTH(d) ((`INST_DLENGTH) & ~32'hFF | (d & 8'hFF))
`define INST_SDI_LANE_MASK (32'h0000_2300 | `SDI_LANE_MASK)
`define SET_SDI_LANE_MASK(m) ((`INST_SDI_LANE_MASK) & ~32'hFF | (m & 8'hFF))
`define INST_SDO_LANE_MASK (32'h0000_2400 | `SDO_LANE_MASK)
`define SET_SDO_LANE_MASK(m) ((`INST_SDO_LANE_MASK) & ~32'hFF | (m & 8'hFF))

// Synchronization
`define INST_SYNC (32'h0000_3000)
Expand Down
16 changes: 8 additions & 8 deletions library/regmaps/adi_regmap_spi_engine_pkg.sv
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Expand Up @@ -42,9 +42,9 @@ package adi_regmap_spi_engine_pkg;
/* SPI Engine (axi_spi_engine) */

const reg_t AXI_SPI_ENGINE_VERSION = '{ 'h0000, "VERSION" , '{
"VERSION_MAJOR": '{ 31, 16, RO, 'h00000001 },
"VERSION_MINOR": '{ 15, 8, RO, 'h00000005 },
"VERSION_PATCH": '{ 7, 0, RO, 'h00000001 }}};
"VERSION_MAJOR": '{ 31, 16, RO, 'h00000002 },
"VERSION_MINOR": '{ 15, 8, RO, 'h00000000 },
"VERSION_PATCH": '{ 7, 0, RO, 'h00000000 }}};
`define SET_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR(x) SetField(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR",x)
`define GET_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR(x) GetField(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR",x)
`define DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR GetResetValue(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR")
Expand Down Expand Up @@ -73,12 +73,12 @@ package adi_regmap_spi_engine_pkg;
`define UPDATE_AXI_SPI_ENGINE_SCRATCH_SCRATCH(x,y) UpdateField(AXI_SPI_ENGINE_SCRATCH,"SCRATCH",x,y)

const reg_t AXI_SPI_ENGINE_DATA_WIDTH = '{ 'h000c, "DATA_WIDTH" , '{
"NUM_OF_SDI": '{ 7, 4, RO, 0 },
"NUM_OF_SDIO": '{ 7, 4, RO, 0 },
"DATA_WIDTH": '{ 3, 0, RO, 0 }}};
`define SET_AXI_SPI_ENGINE_DATA_WIDTH_NUM_OF_SDI(x) SetField(AXI_SPI_ENGINE_DATA_WIDTH,"NUM_OF_SDI",x)
`define GET_AXI_SPI_ENGINE_DATA_WIDTH_NUM_OF_SDI(x) GetField(AXI_SPI_ENGINE_DATA_WIDTH,"NUM_OF_SDI",x)
`define DEFAULT_AXI_SPI_ENGINE_DATA_WIDTH_NUM_OF_SDI GetResetValue(AXI_SPI_ENGINE_DATA_WIDTH,"NUM_OF_SDI")
`define UPDATE_AXI_SPI_ENGINE_DATA_WIDTH_NUM_OF_SDI(x,y) UpdateField(AXI_SPI_ENGINE_DATA_WIDTH,"NUM_OF_SDI",x,y)
`define SET_AXI_SPI_ENGINE_DATA_WIDTH_NUM_OF_SDI(x) SetField(AXI_SPI_ENGINE_DATA_WIDTH,"NUM_OF_SDIO",x)
`define GET_AXI_SPI_ENGINE_DATA_WIDTH_NUM_OF_SDI(x) GetField(AXI_SPI_ENGINE_DATA_WIDTH,"NUM_OF_SDIO",x)
`define DEFAULT_AXI_SPI_ENGINE_DATA_WIDTH_NUM_OF_SDI GetResetValue(AXI_SPI_ENGINE_DATA_WIDTH,"NUM_OF_SDIO")
`define UPDATE_AXI_SPI_ENGINE_DATA_WIDTH_NUM_OF_SDI(x,y) UpdateField(AXI_SPI_ENGINE_DATA_WIDTH,"NUM_OF_SDIO",x,y)
`define SET_AXI_SPI_ENGINE_DATA_WIDTH_DATA_WIDTH(x) SetField(AXI_SPI_ENGINE_DATA_WIDTH,"DATA_WIDTH",x)
`define GET_AXI_SPI_ENGINE_DATA_WIDTH_DATA_WIDTH(x) GetField(AXI_SPI_ENGINE_DATA_WIDTH,"DATA_WIDTH",x)
`define DEFAULT_AXI_SPI_ENGINE_DATA_WIDTH_DATA_WIDTH GetResetValue(AXI_SPI_ENGINE_DATA_WIDTH,"DATA_WIDTH")
Expand Down
36 changes: 22 additions & 14 deletions library/vip/adi/spi_vip/adi_spi_vip.sv
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Expand Up @@ -34,25 +34,29 @@
// ***************************************************************************

module adi_spi_vip #(
parameter MODE = 0, // SLAVE=0
parameter CPOL = 0,
parameter CPHA = 0,
parameter INV_CS = 0,
parameter DATA_DLENGTH = 16,
parameter SLAVE_TIN = 0,
parameter SLAVE_TOUT = 0,
parameter MASTER_TIN = 0,
parameter MASTER_TOUT = 0,
parameter CS_TO_MISO = 0,
parameter MODE = 0, // SLAVE=0
parameter CPOL = 0,
parameter CPHA = 0,
parameter INV_CS = 0,
parameter DATA_DLENGTH = 16,
parameter NUM_OF_SDI = 1,
parameter NUM_OF_SDO = 1,
Comment on lines +42 to +43
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@LBFFilho LBFFilho Aug 8, 2025 •
edited
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Consider renaming these to NUM_OF_MISO/MOSI (or something in this vein), since the VIP could have MOSI as input or output depending on the mode in the future.

parameter SDI_LANE_MASK = 8'hFF,
parameter SDO_LANE_MASK = 8'hFF,
parameter SLAVE_TIN = 0,
parameter SLAVE_TOUT = 0,
parameter MASTER_TIN = 0,
parameter MASTER_TOUT = 0,
parameter CS_TO_MISO = 0,
parameter DEFAULT_MISO_DATA = 'hCAFE
) (
input logic s_spi_sclk,
input logic s_spi_mosi,
output wire s_spi_miso,
input logic [NUM_OF_SDO-1:0] s_spi_mosi,
output wire [NUM_OF_SDI-1:0] s_spi_miso,
input logic s_spi_cs,
output logic m_spi_sclk,
output logic m_spi_mosi,
input wire m_spi_miso,
output logic [NUM_OF_SDO-1:0] m_spi_mosi,
input wire [NUM_OF_SDI-1:0] m_spi_miso,
output logic m_spi_cs
);

Expand All @@ -66,6 +70,10 @@ module adi_spi_vip #(
.CPHA (CPHA),
.INV_CS (INV_CS),
.DATA_DLENGTH (DATA_DLENGTH),
.NUM_OF_SDI (NUM_OF_SDI),
.NUM_OF_SDO (NUM_OF_SDO),
.SDI_LANE_MASK (SDI_LANE_MASK),
.SDO_LANE_MASK (SDO_LANE_MASK),
.SLAVE_TIN (SLAVE_TIN),
.SLAVE_TOUT (SLAVE_TOUT),
.MASTER_TIN (MASTER_TIN),
Expand Down
15 changes: 12 additions & 3 deletions library/vip/adi/spi_vip/adi_spi_vip_if_base_pkg.sv
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Expand Up @@ -35,6 +35,7 @@
package adi_spi_vip_if_base_pkg;

typedef enum {SPI_MODE_SLAVE, SPI_MODE_MASTER, SPI_MODE_MONITOR} spi_mode_t;
typedef logic mosi_array_t [];

virtual class adi_spi_vip_if_base;

Expand All @@ -51,6 +52,14 @@ package adi_spi_vip_if_base_pkg;

pure virtual function int get_param_DATA_DLENGTH();

pure virtual function int get_param_NUM_OF_SDI();

pure virtual function int get_param_NUM_OF_SDO();

pure virtual function int get_param_SDI_LANE_MASK();

pure virtual function int get_param_SDO_LANE_MASK();

pure virtual function int get_param_SLAVE_TIN();

pure virtual function int get_param_SLAVE_TOUT();
Expand All @@ -73,11 +82,11 @@ package adi_spi_vip_if_base_pkg;

pure virtual task wait_for_sample_edge();

pure virtual function logic get_mosi_delayed();
pure virtual function mosi_array_t get_mosi_delayed();

pure virtual task set_miso_drive(bit val);
pure virtual task set_miso_drive(bit val[]);

pure virtual task set_miso_drive_instantaneous(bit val);
pure virtual task set_miso_drive_instantaneous(bit val[]);

pure virtual task wait_for_drive_edge();

Expand Down
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