bori00 / ATM Public

Digital System Design Course (1st year, 2nd Semester)

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Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
Schematics		Schematics
ATM_documentation.pdf		ATM_documentation.pdf
README.md		README.md
accounts.vhd		accounts.vhd
adder_subtractor.vhd		adder_subtractor.vhd
bank-display.vhd		bank-display.vhd
banknotes_ram.vhd		banknotes_ram.vhd
banknotes_unit.vhd		banknotes_unit.vhd
clock_divider.vhd		clock_divider.vhd
comparator.vhd		comparator.vhd
constraint.xdc		constraint.xdc
converter_bcd_to_binary.vhd		converter_bcd_to_binary.vhd
converter_bin_to_bcd.vhd		converter_bin_to_bcd.vhd
counter_with_hold.vhd		counter_with_hold.vhd
counter_with_load.vhd		counter_with_load.vhd
cu.vhd		cu.vhd
d_ff.vhd		d_ff.vhd
debouncer.vhd		debouncer.vhd
display_array_of_banknotes.vhd		display_array_of_banknotes.vhd
dmux_1_7.vhd		dmux_1_7.vhd
dmux_1_to_7_generic.vhd		dmux_1_to_7_generic.vhd
full-adder1.vhd		full-adder1.vhd
full_adder_generic.vhd		full_adder_generic.vhd
jk_ff.vhd		jk_ff.vhd
mux_16_to_1_generic.vhd		mux_16_to_1_generic.vhd
mux_2_to_1.vhd		mux_2_to_1.vhd
mux_2_to_1_generic.vhd		mux_2_to_1_generic.vhd
mux_4_to_1_generic.vhd		mux_4_to_1_generic.vhd
mux_7_1_n.vhd		mux_7_1_n.vhd
mux_7_to_2_generic.vhd		mux_7_to_2_generic.vhd
mux_reg.vhd		mux_reg.vhd
priority_encoder.vhd		priority_encoder.vhd
ram.vhd		ram.vhd
register.vhd		register.vhd
shift_reg_left.vhd		shift_reg_left.vhd
shift_reg_right.vhd		shift_reg_right.vhd
xor.vhd		xor.vhd
xor2.vhd		xor2.vhd

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ATM

Digital System Design project

1st year, 2nd semester