-
Notifications
You must be signed in to change notification settings - Fork 356
Upgrade Vector Support to Latest Spec Version #1010
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
base: master
Are you sure you want to change the base?
Upgrade Vector Support to Latest Spec Version #1010
Conversation
@kgugala not sure who is the main maintainer these days. But you recently had some activity in this repo, so I will tag you here. |
065458a
to
f4ec9b8
Compare
f4ec9b8
to
a9e723b
Compare
So the CI is still failing. The issue is the cache actions on the self hosted runners. The From the
I have upgraded the cache actions to the latest version. This seems to work for the Spike jobs that is run on the GitHub hosted runner, but not on the self-hosted runner. Not sure why exactly, in the logs I can even see that the new version is used.
I have no view into the self hosted runner container, so I am unable to debug this further. I would appreciate it if one of the maintainers could have a look at it. My best guess is that it is an issue with the out of date CentOS 8 container. |
Is someone reviewing this? |
wrong PR, please ignore |
This PR upgrades the existing vector support from ~v0.7 to the ratified vector spec v1.0. A lot has changed since v0.7, so this is basically a complete rewrite of the vector setup. I think basically every single vector relevant line has been touched.
I am very sorry for the massive PR. But at this point it is too late to properly split it up into smaller chunks. And I think most (if not all) changes need to go in at the same time to make sense and not break the existing tool. I hope we can get it reviewed regardless and get this PR merged!
This PR includes the following changes:
vtype
)vset[i]vl[i]
interleaving into instruction stream (does not work with simultaneous directed scenarios)Zvl<vl>b
,Zvfhmin
, andZvfh
extensions.The vector support has been designed such that all vector instructions will be valid. Meaning they are constrained that no instruction will throw an illegal instruction exception and no vector load/store instruction will throw a page/access/unaligned exception fault.
Regarding linting, I have run variable-lint and there are a few remaining line length warnings. How strongly is this enforced? There were also other warnings that were unrelated to my changes (some of which I have fixed), so does it need to be variable-lint clean to merge this PR?
I hope we can get this PR merged. We have had very good experience with the changes and the tool in general. It has uncovered a huge amount of bugs during our verification efforts, both in our custom IP and third party IPs. A lot of issues we would never had uncovered if we had to write custom test cases. So I still see a huge amount of value in RISCV-DV. And these changes hope to improve the tool even further.