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Added parallelism to euvm port #917

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@puneet puneet commented Nov 30, 2022

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puneet added 30 commits November 24, 2022 22:29
@puneet
Fixed some syntactic style inconsistencies
38b35f6
@puneet
Fixed s core setting parameter as enum
3e06f91
@puneet
Added makefile target for pmp test
41b7e80
@puneet
Uncommented a "solve before" constraint that was inadvertantly commneted
0ccd6f0
@puneet
Fixed an issue with pmp configuration
85fecec
@puneet
Misc fixes
008921f
@puneet
Fizes for 32 bit RISCV
45072b9
@puneet
Added and used append and prepend functions for instr_list
5eb63d8
@puneet
Create and use new class riscv_prog_instr_stream
e432b45
@puneet
Refactored mixing of directed instructions in the prog instr_list
83ab325
@puneet
Use forked parallism while generating big chuck of instrutions
da1b945
@puneet
Generate directed stream on multiple cores
d782a64
@puneet
Add parallelization parameters to config and use these
9161dc9
@puneet
Fixed compilation issues
0f087ac
@puneet
fixes in makefile
21f000d
@puneet
Fix imm_str for performance
59a7425
@puneet
Tag overriding constraint with constraint_override
6cd7f5e
@puneet
Add command line options for par_num_threads and par_instr_threshold
9bb0f9f
@puneet
Fixed instruction randomization for performance
3c76ed3
@puneet
Disable GC when the instruction dump is generated
9010aca
@puneet
Add constraint_override tag for overriding constraint
f04f41d
@puneet
Pass command line config for par_num_threads to riscv-dv config
aaa4680
@puneet
Add compile optiond for LTO
ed12769
@puneet
Rearrange instr sequence to avoid push_front
6faee00 
Just so that we can try using array in place of Queue
@puneet
Fix atomicity os subprogram calls
8c09cf9
@puneet
Fix riscv_instr_test
e7a7baf
@puneet
Use format in place of format_string
8d52ad0
@puneet
Renamed string enum indent as INDENT
9da703a
@puneet
Use ScratchPad to enable faster convert2asm functionality
957107a
@puneet
Fix directed stream naming
e4e14f7
puneet and others added 29 commits January 10, 2024 01:27
@puneet
[euvm] [pmp] Store and load faults caused by locked PMP regions now s…
0d33f94 
…kip to next instruction
@puneet
[euvm] [pmp] Try to skip instruction if no PMP match and in MMWP
59d48d5
@puneet
[euvm] [pmp] Add illegal TOR and NAPOT address mode constraints
7dce3ea
@puneet
[euvm] [pmp] Add a register for loop counter in PMP traps instead of …
5061582 
…mscratch
@puneet
[euvm] [pmp] Improve formatting of PMP addresses for debug
ac7f02f
@puneet
[euvm] [pmp] Fix plusarg detection for MML and MMWP
7c00fda
@puneet
[euvm] Store user-stack-pointer on kernel stack when pushing/popping …
8377f24 
…GPRs
@puneet
[euvm] Reserve one extra word when pushing GPRs to kernel stack
a11bb49
@puneet
[euvm] Fixed wrong length of I, S, B-type immediates causing wrong si…
f0a4179 
…gn extension for certain instructions
@puneet
[euvm] Issue chipsalliance#778 fix, change mie behavior in setup_mmod…
8d3f233 
…e_reg
@puneet
[euvm] randomizing mstatus.MIE when priv mode is lower than machine
8d1f8ca
@puneet
[euvm] Fix for issue chipsalliance#826, illegal rs1 in C_JALR
a01579a
@puneet
[euvm] [pmp] Add option to constrain addresses to stay in 32-bit space
b40c187
@puneet
[euvm] [pmp] Ensure MML PMP configurations don't dominate.
998c0c4
@puneet
[euvm] [Page Table]Fix issue#926 issue#846, NEXT_LEVEL_PAGE entry's a…
feb9a73 
…,d,u should be 0
@puneet
[euvm] [pmp] Remove MSECCFG reads from trap handler when Smepmp is di…
07ef0d0 
…sabled
@puneet
[euvm] Prefer using UBVEC than toubvec for constant bvec values
21d87d1
@puneet
All vector instructions are now registered individually
bf6b484 
Earlier the base vector instruction was registered along with possible variants
@mkurc-ant @puneet
Fixes to support RV32
170b5db 
Signed-off-by: Maciej Kurc <[email protected]>
@puneet
First step towards converging with riscv-opcodes project
334fba5
@puneet
Use tallocator for fast multicode memory allocations
2ae196d
@puneet
Added partial support for riscv opcodes package
6fe39f9
@puneet
Fixes for 32 bit RISCV
f170d0c
@mkurc-ant @puneet
Fixes to support RV32
ef040f4 
Signed-off-by: Maciej Kurc <[email protected]>
@puneet
Fixes for 32 bit RISCV
ce01c2f
@puneet
Added p-extension instructions to gen/isa
29ce0e9
@puneet
Added rv64imp as target
e44b7a3
@puneet
Converged with the riscv-opcode project
a7a56c7
@puneet
Fixed some compilation issues
4a68deb
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3 participants

@puneet @eszpotanski @mkurc-ant