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There is a bug in the instruction function coverage. The store rs1 an… #920

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There is a bug in the instruction function coverage. The store rs1 an… #920

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10 changes: 5 additions & 5 deletions src/isa/riscv_instr_cov.svh
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Original file line number Diff line number Diff line change
Expand Up @@ -290,11 +290,11 @@
S_FORMAT, B_FORMAT: begin
`DV_CHECK_FATAL(operands.size() == 3)
if(category == STORE) begin
// store rs2, imm(rs1) -> rs1,rs2,imm
rs2 = get_gpr(operands[1]);
rs2_value = get_gpr_state(operands[1]);
rs1 = get_gpr(operands[0]);
rs1_value = get_gpr_state(operands[0]);
// store rs2, imm(rs1) -> rs2,rs1,imm
rs2 = get_gpr(operands[0]);
rs2_value = get_gpr_state(operands[0]);
rs1 = get_gpr(operands[1]);
rs1_value = get_gpr_state(operands[1]);
get_val(operands[2], imm);
end else begin
// bne rs1, rs2, imm
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