Logo by Tokino Kei.
Sentinel is a small RISC-V CPU (RV32I_Zicsr) written in Amaranth.
It implements the Machine Mode privileged spec, and is designed to fit into
~1000 4-input LUTs or less on an FPGA. It is a good candidate for control tasks
where a programmable state machine or custom size-tailored core would otherwise
be used.
Unlike most RISC-V implementations, Sentinel is microcoded, not pipelined. Instructions require multiple clock cycles to execute. Sentinel is therefore not necessarily a good fit for applications where high throughput/ IPC is required. Short version: minimum of 4 CPI for basic arithmetic, maximum of 69 for a 31-bit shift (yes, shift instructions need work).
As of 5-9-2026, development has moved to Codeberg. Please update your remotes. This repository is not currently mirrored.