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SH-2E CPU implementation#104

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MatusJurcak wants to merge 73 commits into
d-iii-s:masterfrom
MatusJurcak:master
Open

SH-2E CPU implementation#104
MatusJurcak wants to merge 73 commits into
d-iii-s:masterfrom
MatusJurcak:master

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@MatusJurcak

@MatusJurcak MatusJurcak commented Mar 14, 2026 •
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This pull request adds support for the SH-2E CPU to MSIM.

Main changes include:

  • Implementation of the SH-2E CPU
  • Addition of a new INTC device required for the SH-2E implementation
  • Updates to byte and word physical memory write handling
  • Option for the printer device to operate in big-endian mode
  • Tests covering all SH-2E instructions and exception handling
  • Clang format changes
  • Updated documentation for the CPU, INTC and printer

Changes added in the second batch:

  • New devices: CMT, WDT and DMAC
  • Updated documentation for the new devices
  • Basic tests covering interrupts from these devices

lbulej and others added 30 commits February 16, 2026 22:04
@lbulej @MatusJurcak
Fix typos in comments
9f1e731
@lbulej @MatusJurcak
Do not initialize ftl0 explicitly
aa38634 
The array goes into BSS and will be zeroed anyway.
@lbulej @MatusJurcak
Add array_len and offset_of to utils.h
da5ea5a
@lbulej @MatusJurcak
Use array_len() instead of DEVICE_TYPE_COUNT to search device_types
111c22b 
No need to worry about updating DEVICE_TYPE_COUNT when adding new
devices.
@lbulej @MatusJurcak
SH-2E implementation
3c6e967
@lbulej @MatusJurcak
SH-2E integration with MSIM
acbbed8
@lbulej @MatusJurcak
SH-2E clang-format configuration
0a01fb9
@lbulej @MatusJurcak
SH-2E helper scripts
a26a96e
@lbulej @MatusJurcak
SH-2E sample msim.conf
e25a12f
@MatusJurcak
SH-2E add few unimplemented instructions + cstyle fix
5eff654
@MatusJurcak
SH-2E LDC/LDS instructions implementation
8052b66
@MatusJurcak
SH-2E add HALT and CPU_REG_DUMP instructions for MSIM + fix address c…
9a5cf8c 
…omputing for MOVI instructions
@MatusJurcak
SH-2E FPU registers dump instruction + fix fpscr register for little …
51efa9d 
…endian
@MatusJurcak
SH-2E fix printer to work with big endian order
17f0e50
@MatusJurcak
SH-2E interrupt/exception handling + INTC
5ea7461
@MatusJurcak
SH-2E fix PC value when pushing to stack on interrupt handling
72ad30b
@MatusJurcak
SH-2E add option to confiure INTC registers addresses
e9949a3
@MatusJurcak
SH-2E make INTC dynamic and configurable + rework exception processin…
4e23ae2 
…g, add checks for alignment and add basic accounting
@MatusJurcak
SH-2E remove limit on number of interrupt sources
dbdf1a5
@MatusJurcak
SH-2E make INTC independent device
37349df 
This commit makes the INTC as its own independent device and also changes the SH-2E CPU step behaviour.
Now the CPU step mimicks one step in the CPU state automaton instead of executing one instruction per step.
@MatusJurcak
SH-2E add support for power-on/manual resets
d53f6b1
@MatusJurcak
SH-2E add reference between INTC and CPU
dbfeb14 
Added reference between SH-2E cpu and interrupt controller.
Changed the resets behaviour to be similiar to interrupt sources.
Also added some example configuration to the msim.conf file.
@MatusJurcak
SH-2E Add debug functions for other processing states
15a3495
@MatusJurcak
SH-2E Add unit tests and simple test
aa6e7e7
@MatusJurcak
SH-2E Add unit tests for exceptions
12ae520
@MatusJurcak
SH-2E Refactor instruction opcodes
6946b8d
@MatusJurcak
SH-2E Fix nd4 format in utils
92ab902
@MatusJurcak
SH-2E FDIV and FMAC exceptions
9491a8d
@MatusJurcak
SH-2E Fix the FADD insn
d96af82
@MatusJurcak
SH-2E Add test with C file and fix printing
4302c15
lbulej
lbulej reviewed May 25, 2026
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Comment thread src/device/cpu/superh_sh2e/cpu.h Outdated
@lbulej

lbulej commented May 27, 2026

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Maybe just one final bit, I would rather see pc_next + sizeof(sh2e_insn_t) than just pc_next + 2 in the code (several places). The outcome is the same, but it says it bumps the PC by one instruction.

I know they don't do it like that even in the manual, but it's a documentation bit that does not cost anything.

Similarly for cases with pc + 4 => pc + 2 * sizeof(sh2e_insn_t).

lbulej
lbulej reviewed May 29, 2026
View reviewed changes
Comment thread src/device/cpu/superh_sh2e/disasm.c Outdated
lbulej
lbulej reviewed May 29, 2026
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Comment thread src/device/cpu/superh_sh2e/disasm.c Outdated
lbulej
lbulej reviewed May 29, 2026
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Comment thread src/device/cpu/superh_sh2e/exec.c Outdated
lbulej
lbulej reviewed May 29, 2026
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Comment thread src/device/cpu/superh_sh2e/exec.c Outdated
lbulej
lbulej reviewed May 29, 2026
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Comment thread src/device/cpu/superh_sh2e/exec.c Outdated
lbulej
lbulej reviewed May 29, 2026
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Comment thread src/device/cpu/superh_sh2e/exec.c Outdated
@lbulej

lbulej commented Jun 10, 2026

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The physmem endianness is quite intrusive, I would separate it to another PR. Things generally work in this PR, so I think the refactor can go in separately.

@MatusJurcak

MatusJurcak commented Jun 11, 2026

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I removed the last commit regarding the physmem refactor and I just left the fixes to the peripheral devices. I'll make another PR after we merge this one, as the physmem changes would also affect all the PRs that are open right now.

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@MatusJurcak @vhotspur @lbulej