WIP: Support PXIe-EVR-300

[mdavidsaver]

Add support for PXIe-EVR-300 card.

Open issues/questions:

• Control[LMEDE] bit settable, but has no effect as of FW 0x16220207. Always big endian.
  • Firmware fix?
  • Remove HACK to always use BE access. set the undocumented Control[1] bit.
• Handle discontiguous input control register range(s)
• Clarify I vs. U board variants
• Confirm input/output pin mappings
• Add OPI screen

[mdavidsaver]

This card has an impressive number of backplane connections. 59x outputs and 42x inputs. Excerpting from the MRF manual EVR-MRM-008 21 May 2024:

I do not find where the TBIN* control registers are located.

[mdavidsaver]

Testing with firmware 0x16220207 shows that the endian control bit has no effect. This firmware is "stuck" with big endian order. This branch includes a temporary hack to switch all PCI access to BE to facilitate further testing. I think a firmware update will be needed.

eg. on an x86_64 host:

epics> pciread 32 0 0x30

0x00000000 00008100 02000002 05000000 00000000
0x00000010 00000000 00000000 00000000 00000000
0x00000020 00100000 00001100 00001100 07022216
epics> pciwrite 32 4 0          
epics> pciread 32 0 0x30

0x00000000 00008100 00000000 05000000 00000000
0x00000010 00000000 00000000 00000000 00000000
0x00000020 00100000 00001100 00001100 07022216
epics>

[jerzyjamroz]

• Where are the TBIN[0:41] control registers located?

I do not use PXIe EVR but I guess it is:

{"\$(P)InRear0",  "$(EVR):FPIn48", "InTB0 (UNIV)"}
{"\$(P)InRear1",  "$(EVR):FPIn49", "InTB1 (UNIV)"}
{"\$(P)InRear2",  "$(EVR):FPIn50", "InTB2 (UNIV)"}
{"\$(P)InRear3",  "$(EVR):FPIn51", "InTB3 (UNIV)"}
{"\$(P)InRear4",  "$(EVR):FPIn52", "InTB4 (UNIV)"}
{"\$(P)InRear5",  "$(EVR):FPIn53", "InTB5 (UNIV)"}
{"\$(P)InRear6",  "$(EVR):FPIn54", "InTB6 (UNIV)"}
{"\$(P)InRear7",  "$(EVR):FPIn55", "InTB7 (UNIV)"}
{"\$(P)InRear8",  "$(EVR):FPIn56", "InTB8 (UNIV)"}
{"\$(P)InRear9",  "$(EVR):FPIn57", "InTB9 (UNIV)"}

P.S.
I was thinking in the past to rewrite/upgrade the input management (similar to outputs), but it works so...

[jerzyjamroz]

• Add OPI screen

There is a list of the project sub-suports.

[jerzyjamroz]

eg. on an x86_64 host:

It misses one test, so to write explicitly the initial configuration and readout (It might be that it is an inverted implementation of LEMDE).

[mdavidsaver]

Testing with firmware 0x16220207 shows that the endian control bit has no effect.

A firmware update 0x16232007 mostly corrects Control[LMEDE]. It is still necessary to write 0x02000002, both bits, to get an effect.

• Where are the TBIN[0:41] control registers located?

I do not use PXIe EVR but I guess it is:

Sorry, I was imprecise. The issue is that there is only space for 32x input control registers between 0x500 and 0x580. The PXIe-EVR-300 has 48x inputs to control. Jukka deals with this by by splitting the input control around the GTX*Dly registers. So the range is not contiguous.