Arduino ESP32 v3.3 based on ESP-IDF v5.5 (master)

.github/scripts/on-push.sh

@@ -90,6 +90,7 @@ if [ "$BUILD_LOG" -eq 1 ]; then
 fi
 
 #build sketches for different targets
+build "esp32c5" "$CHUNK_INDEX" "$CHUNKS_CNT" "$BUILD_LOG" "$LOG_LEVEL" "$SKETCHES_FILE" "${SKETCHES_ESP32[@]}"
 build "esp32p4" "$CHUNK_INDEX" "$CHUNKS_CNT" "$BUILD_LOG" "$LOG_LEVEL" "$SKETCHES_FILE" "${SKETCHES_ESP32[@]}"
 build "esp32s3" "$CHUNK_INDEX" "$CHUNKS_CNT" "$BUILD_LOG" "$LOG_LEVEL" "$SKETCHES_FILE" "${SKETCHES_ESP32[@]}"
 build "esp32s2" "$CHUNK_INDEX" "$CHUNKS_CNT" "$BUILD_LOG" "$LOG_LEVEL" "$SKETCHES_FILE" "${SKETCHES_ESP32[@]}"

.github/scripts/sketch_utils.sh

@@ -156,6 +156,7 @@ function build_sketch { # build_sketch <ide_path> <user_path> <path-to-ino> [ext
             esp32c6_opts=$(echo "$debug_level,$fqbn_append" | sed 's/^,*//;s/,*$//;s/,\{2,\}/,/g')
             esp32h2_opts=$(echo "$debug_level,$fqbn_append" | sed 's/^,*//;s/,*$//;s/,\{2,\}/,/g')
             esp32p4_opts=$(echo "PSRAM=enabled,USBMode=default,$debug_level,$fqbn_append" | sed 's/^,*//;s/,*$//;s/,\{2,\}/,/g')
+            esp32c5_opts=$(echo "$debug_level,$fqbn_append" | sed 's/^,*//;s/,*$//;s/,\{2,\}/,/g')
 
             # Select the common part of the FQBN based on the target.  The rest will be
             # appended depending on the passed options.
@@ -191,6 +192,10 @@ function build_sketch { # build_sketch <ide_path> <user_path> <path-to-ino> [ext
                     [ -n "${options:-$esp32p4_opts}" ] && opt=":${options:-$esp32p4_opts}"
                     fqbn="espressif:esp32:esp32p4$opt"
                 ;;
+                "esp32c5")
+                    [ -n "${options:-$esp32c5_opts}" ] && opt=":${options:-$esp32c5_opts}"
+                    fqbn="espressif:esp32:esp32c5$opt"
+                ;;
                 *)
                     echo "ERROR: Invalid chip: $target"
                     exit 1

.github/workflows/push.yml

@@ -47,6 +47,7 @@ on:
       - "variants/esp32/**/*"
       - "variants/esp32c2/**/*"
       - "variants/esp32c3/**/*"
+      - "variants/esp32c5/**/*"
       - "variants/esp32c6/**/*"
       - "variants/esp32h2/**/*"
       - "variants/esp32p4/**/*"

CMakeLists.txt

@@ -6,7 +6,7 @@
 #   idf.py build
 
 set(min_supported_idf_version "5.3.0")
-set(max_supported_idf_version "5.4.99")
+set(max_supported_idf_version "5.5.99")
 set(idf_version "${IDF_VERSION_MAJOR}.${IDF_VERSION_MINOR}.${IDF_VERSION_PATCH}")
 
 if ("${idf_version}" AND NOT "$ENV{ARDUINO_SKIP_IDF_VERSION_CHECK}")

boards.txt

@@ -161,6 +161,217 @@ esp32c2.menu.EraseFlash.all.upload.erase_cmd=-e
 
 ##############################################################
 
+esp32c5.name=ESP32C5 Dev Module
+
+esp32c5.bootloader.tool=esptool_py
+esp32c5.bootloader.tool.default=esptool_py
+
+esp32c5.upload.tool=esptool_py
+esp32c5.upload.tool.default=esptool_py
+esp32c5.upload.tool.network=esp_ota
+
+esp32c5.upload.maximum_size=1310720
+esp32c5.upload.maximum_data_size=327680
+esp32c5.upload.flags=
+esp32c5.upload.extra_flags=
+esp32c5.upload.use_1200bps_touch=false
+esp32c5.upload.wait_for_upload_port=false
+
+esp32c5.serial.disableDTR=false
+esp32c5.serial.disableRTS=false
+
+esp32c5.build.tarch=riscv32
+esp32c5.build.target=esp
+esp32c5.build.mcu=esp32c5
+esp32c5.build.core=esp32
+esp32c5.build.variant=esp32c5
+esp32c5.build.board=ESP32C5_DEV
+esp32c5.build.bootloader_addr=0x2000
+
+esp32c5.build.cdc_on_boot=0
+esp32c5.build.f_cpu=240000000L
+esp32c5.build.flash_size=4MB
+esp32c5.build.flash_freq=80m
+esp32c5.build.flash_mode=qio
+esp32c5.build.boot=qio
+esp32c5.build.partitions=default
+esp32c5.build.defines=
+
+## IDE 2.0 Seems to not update the value
+esp32c5.menu.JTAGAdapter.default=Disabled
+esp32c5.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32c5.menu.JTAGAdapter.builtin=Integrated USB JTAG
+esp32c5.menu.JTAGAdapter.builtin.build.openocdscript=esp32c5-builtin.cfg
+esp32c5.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+esp32c5.menu.JTAGAdapter.external=FTDI Adapter
+esp32c5.menu.JTAGAdapter.external.build.openocdscript=esp32c5-ftdi.cfg
+esp32c5.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32c5.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32c5.menu.JTAGAdapter.bridge.build.openocdscript=esp32c5-bridge.cfg
+esp32c5.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32c5.menu.PSRAM.disabled=Disabled
+esp32c5.menu.PSRAM.disabled.build.defines=
+esp32c5.menu.PSRAM.enabled=Enabled
+esp32c5.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+
+esp32c5.menu.CDCOnBoot.default=Disabled
+esp32c5.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32c5.menu.CDCOnBoot.cdc=Enabled
+esp32c5.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32c5.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32c5.menu.PartitionScheme.default.build.partitions=default
+esp32c5.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32c5.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32c5.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32c5.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32c5.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32c5.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32c5.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32c5.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+esp32c5.menu.PartitionScheme.no_fs.build.partitions=no_fs
+esp32c5.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+esp32c5.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32c5.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32c5.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32c5.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32c5.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32c5.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32c5.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32c5.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32c5.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32c5.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32c5.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32c5.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32c5.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32c5.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32c5.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32c5.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32c5.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32c5.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32c5.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32c5.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32c5.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32c5.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32c5.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32c5.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32c5.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32c5.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32c5.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32c5.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32c5.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32c5.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32c5.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32c5.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32c5.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32c5.menu.PartitionScheme.zigbee_2MB=Zigbee 2MB with spiffs
+esp32c5.menu.PartitionScheme.zigbee_2MB.build.partitions=zigbee_2MB
+esp32c5.menu.PartitionScheme.zigbee_2MB.upload.maximum_size=1310720
+esp32c5.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+esp32c5.menu.PartitionScheme.zigbee.build.partitions=zigbee
+esp32c5.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+esp32c5.menu.PartitionScheme.zigbee_8MB=Zigbee 8MB with spiffs
+esp32c5.menu.PartitionScheme.zigbee_8MB.build.partitions=zigbee_8MB
+esp32c5.menu.PartitionScheme.zigbee_8MB.upload.maximum_size=3407872
+esp32c5.menu.PartitionScheme.zigbee_zczr_2MB=Zigbee ZCZR 2MB with spiffs
+esp32c5.menu.PartitionScheme.zigbee_zczr_2MB.build.partitions=zigbee_zczr_2MB
+esp32c5.menu.PartitionScheme.zigbee_zczr_2MB.upload.maximum_size=1310720
+esp32c5.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+esp32c5.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+esp32c5.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+esp32c5.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs
+esp32c5.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB
+esp32c5.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872
+esp32c5.menu.PartitionScheme.custom=Custom
+esp32c5.menu.PartitionScheme.custom.build.partitions=
+esp32c5.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32c5.menu.CPUFreq.240=240MHz (WiFi)
+esp32c5.menu.CPUFreq.240.build.f_cpu=240000000L
+esp32c5.menu.CPUFreq.120=120MHz (WiFi)
+esp32c5.menu.CPUFreq.120.build.f_cpu=120000000L
+esp32c5.menu.CPUFreq.80=80MHz (WiFi)
+esp32c5.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32c5.menu.CPUFreq.40=40MHz
+esp32c5.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32c5.menu.CPUFreq.20=20MHz
+esp32c5.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32c5.menu.CPUFreq.10=10MHz
+esp32c5.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32c5.menu.FlashMode.qio=QIO
+esp32c5.menu.FlashMode.qio.build.flash_mode=dio
+esp32c5.menu.FlashMode.qio.build.boot=qio
+esp32c5.menu.FlashMode.dio=DIO
+esp32c5.menu.FlashMode.dio.build.flash_mode=dio
+esp32c5.menu.FlashMode.dio.build.boot=dio
+
+esp32c5.menu.FlashFreq.80=80MHz
+esp32c5.menu.FlashFreq.80.build.flash_freq=80m
+esp32c5.menu.FlashFreq.40=40MHz
+esp32c5.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32c5.menu.FlashSize.4M=4MB (32Mb)
+esp32c5.menu.FlashSize.4M.build.flash_size=4MB
+esp32c5.menu.FlashSize.8M=8MB (64Mb)
+esp32c5.menu.FlashSize.8M.build.flash_size=8MB
+esp32c5.menu.FlashSize.2M=2MB (16Mb)
+esp32c5.menu.FlashSize.2M.build.flash_size=2MB
+esp32c5.menu.FlashSize.16M=16MB (128Mb)
+esp32c5.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32c5.menu.UploadSpeed.921600=921600
+esp32c5.menu.UploadSpeed.921600.upload.speed=921600
+esp32c5.menu.UploadSpeed.115200=115200
+esp32c5.menu.UploadSpeed.115200.upload.speed=115200
+esp32c5.menu.UploadSpeed.256000.windows=256000
+esp32c5.menu.UploadSpeed.256000.upload.speed=256000
+esp32c5.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32c5.menu.UploadSpeed.230400=230400
+esp32c5.menu.UploadSpeed.230400.upload.speed=230400
+esp32c5.menu.UploadSpeed.460800.linux=460800
+esp32c5.menu.UploadSpeed.460800.macosx=460800
+esp32c5.menu.UploadSpeed.460800.upload.speed=460800
+esp32c5.menu.UploadSpeed.512000.windows=512000
+esp32c5.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32c5.menu.DebugLevel.none=None
+esp32c5.menu.DebugLevel.none.build.code_debug=0
+esp32c5.menu.DebugLevel.error=Error
+esp32c5.menu.DebugLevel.error.build.code_debug=1
+esp32c5.menu.DebugLevel.warn=Warn
+esp32c5.menu.DebugLevel.warn.build.code_debug=2
+esp32c5.menu.DebugLevel.info=Info
+esp32c5.menu.DebugLevel.info.build.code_debug=3
+esp32c5.menu.DebugLevel.debug=Debug
+esp32c5.menu.DebugLevel.debug.build.code_debug=4
+esp32c5.menu.DebugLevel.verbose=Verbose
+esp32c5.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32c5.menu.EraseFlash.none=Disabled
+esp32c5.menu.EraseFlash.none.upload.erase_cmd=
+esp32c5.menu.EraseFlash.all=Enabled
+esp32c5.menu.EraseFlash.all.upload.erase_cmd=-e
+
+esp32c5.menu.ZigbeeMode.default=Disabled
+esp32c5.menu.ZigbeeMode.default.build.zigbee_mode=
+esp32c5.menu.ZigbeeMode.default.build.zigbee_libs=
+esp32c5.menu.ZigbeeMode.ed=Zigbee ED (end device)
+esp32c5.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+esp32c5.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+esp32c5.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+esp32c5.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+esp32c5.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+esp32c5.menu.ZigbeeMode.ed_debug=Zigbee ED (end device) - Debug
+esp32c5.menu.ZigbeeMode.ed_debug.build.zigbee_mode=-DZIGBEE_MODE_ED
+esp32c5.menu.ZigbeeMode.ed_debug.build.zigbee_libs=-lesp_zb_api.ed.debug -lzboss_stack.ed.debug -lzboss_port.native.debug
+esp32c5.menu.ZigbeeMode.zczr_debug=Zigbee ZCZR (coordinator/router) - Debug
+esp32c5.menu.ZigbeeMode.zczr_debug.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+esp32c5.menu.ZigbeeMode.zczr_debug.build.zigbee_libs=-lesp_zb_api.zczr.debug -lzboss_stack.zczr.debug -lzboss_port.native.debug
+
+##############################################################
+
 esp32p4.name=ESP32P4 Dev Module
 
 esp32p4.bootloader.tool=esptool_py

cores/esp32/Esp.cpp

@@ -21,6 +21,7 @@
 #include "Esp.h"
 #include "esp_sleep.h"
 #include "spi_flash_mmap.h"
+#include "esp_idf_version.h"
 #include <memory>
 #include <soc/soc.h>
 #include <esp_partition.h>
@@ -63,6 +64,9 @@ extern "C" {
 #elif CONFIG_IDF_TARGET_ESP32P4
 #include "esp32p4/rom/spi_flash.h"
 #define ESP_FLASH_IMAGE_BASE 0x2000  // Esp32p4 is located at 0x2000
+#elif CONFIG_IDF_TARGET_ESP32C5
+#include "esp32c5/rom/spi_flash.h"
+#define ESP_FLASH_IMAGE_BASE 0x2000  // Esp32c5 is located at 0x2000
 #else
 #error Target CONFIG_IDF_TARGET is not supported
 #endif
@@ -301,7 +305,12 @@ const char *EspClass::getChipModel(void) {
     case CHIP_ESP32C6: return "ESP32-C6";
     case CHIP_ESP32H2: return "ESP32-H2";
     case CHIP_ESP32P4: return "ESP32-P4";
-    default:           return "UNKNOWN";
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0)
+    case CHIP_ESP32C5:  return "ESP32-C5";
+    case CHIP_ESP32C61: return "ESP32-C61";
+    case CHIP_ESP32H21: return "ESP32-H21";
+#endif
+    default: return "UNKNOWN";
   }
 #endif
 }

cores/esp32/HardwareSerial.h

@@ -139,6 +139,8 @@ typedef enum {
 #define SOC_RX0 (gpio_num_t)23
 #elif CONFIG_IDF_TARGET_ESP32P4
 #define SOC_RX0 (gpio_num_t)38
+#elif CONFIG_IDF_TARGET_ESP32C5
+#define SOC_RX0 (gpio_num_t)12
 #endif
 #endif
 
@@ -157,6 +159,8 @@ typedef enum {
 #define SOC_TX0 (gpio_num_t)24
 #elif CONFIG_IDF_TARGET_ESP32P4
 #define SOC_TX0 (gpio_num_t)37
+#elif CONFIG_IDF_TARGET_ESP32C5
+#define SOC_TX0 (gpio_num_t)11
 #endif
 #endif
 
@@ -180,6 +184,8 @@ typedef enum {
 #define RX1 (gpio_num_t)0
 #elif CONFIG_IDF_TARGET_ESP32P4
 #define RX1 (gpio_num_t)11
+#elif CONFIG_IDF_TARGET_ESP32C5
+#define RX1 (gpio_num_t)4
 #endif
 #endif
 
@@ -200,6 +206,8 @@ typedef enum {
 #define TX1 (gpio_num_t)1
 #elif CONFIG_IDF_TARGET_ESP32P4
 #define TX1 (gpio_num_t)10
+#elif CONFIG_IDF_TARGET_ESP32C5
+#define TX1 (gpio_num_t)5
 #endif
 #endif
 #endif /* SOC_UART_HP_NUM > 1 */

cores/esp32/chip-debug-report.cpp

@@ -67,6 +67,9 @@ static void printPkgVersion(void) {
 #elif CONFIG_IDF_TARGET_ESP32P4
   uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS_2_REG, EFUSE_PKG_VERSION);
   chip_report_printf("%lu", pkg_ver);
+#elif CONFIG_IDF_TARGET_ESP32C5
+  uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS2_REG, EFUSE_PKG_VERSION);
+  chip_report_printf("%lu", pkg_ver);
 #else
   chip_report_printf("Unknown");
 #endif
@@ -88,6 +91,11 @@ static void printChipInfo(void) {
     case CHIP_ESP32C6: chip_report_printf("ESP32-C6\n"); break;
     case CHIP_ESP32H2: chip_report_printf("ESP32-H2\n"); break;
     case CHIP_ESP32P4: chip_report_printf("ESP32-P4\n"); break;
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0)
+    case CHIP_ESP32C5: chip_report_printf("ESP32-C5\n"); break;
+    case CHIP_ESP32C61: chip_report_printf("ESP32-C61\n"); break;
+    case CHIP_ESP32H21: chip_report_printf("ESP32-H21\n"); break;
+#endif
     default:           chip_report_printf("Unknown %d\n", info.model); break;
   }
   printPkgVersion();