fix(openeth): fix cache-off panic in IRAM ISR handler (IDFGH-17705)

[vvzvlad]

Description
emac_opencores_isr_handler is registered with ESP_INTR_FLAG_IRAM and marked IRAM_ATTR, meaning it must not access flash-backed memory while the cache is disabled. However, the handler contained:

ESP_EARLY_LOGW(TAG, "%s: RX frame dropped (0x%" PRIx32 ")", func, status);
This is not cache-off-safe:

TAG (static const char *TAG = "opencores.emac") sits in .rodata → flash
func is also a flash-resident string
ESP_EARLY_LOGW eventually calls uart_hal_write_txfifo, which lives in flash (IROM) unless CONFIG_UART_ISR_IN_IRAM=y
When OPENETH_INT_BUSY fires while another task has the cache disabled (e.g. during esp_partition_read), the firmware panics:

Guru Meditation Error: Core 0 panic'ed (Cache disabled but cached memory region accessed).
EXCCAUSE: 0x00000007
Fix:

Declare TAG as static const DRAM_ATTR char TAG[] to place the string in DRAM
Replace ESP_EARLY_LOGW with ESP_DRAM_LOGW (the correct macro for cache-off ISR context)
Remove the func argument (flash string) from the log call

Related
Reproducer (synthetic, no networking, deterministic): openeth_repro/ — registers an ESP_INTR_FLAG_IRAM SW interrupt mirroring the openeth ISR body, and concurrently hammers esp_partition_read to disable the cache. Crashes within seconds on unpatched code; runs indefinitely with this fix.

Measurements (ESP32, IDF v5.4, qemu-system-xtensa):

Build Crashes / 30 s ISR fires before crash
Upstream (buggy) 6 ~191
This patch 0 27 636+

Issue: #18644

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