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These are a few cores I have created recently to get openrisc instruction traces working with Verilator. These are used in mor1kx-generic with:

fusesoc run --target mor1kx_tb --tool varilator mor1kx-generic \
  --elf_load ./openrisc-asm --trace_enable

Note, with icarus backend there is a monitor Verilog module that does this using Verilog system tasks/functions.

This ads a new utility to detect a clock posEdge.
A new module used by mor1kx-generic to provide OpenRISC instruction
traces in verilator.

Link: https://github.com/stffrdhrn/mor1kx-generic
@stffrdhrn
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Hi @olofk , these are two core updates. I understand if you don't think or1ksim_trace belongs in this official repo and all. I would appreciate you having a look.

Has fixes for verilator and new parameters to allow
configuraing core synth options via fusesoc command line params.
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