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[GSoC] Updated DC-DC Verilog Generation and Simulations #230

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3b22652
feat: use the new verilog generation module in dcdc-gen
harshkhandeparkar Jun 12, 2023
6a9b124
fix: return stringified powmux_config
harshkhandeparkar Jun 12, 2023
fc8fca9
feat: update dcdc-gen verilog to use Mako syntax
harshkhandeparkar Jun 12, 2023
5b89116
feat: gitignore generated verilog in dcdc-gen
harshkhandeparkar Jun 12, 2023
8f7b28d
feat: remove unused code in dcdc_gen.py
harshkhandeparkar Jun 12, 2023
2c18599
feat: added a command to make clean to remove generated verilog in dc…
harshkhandeparkar Jun 12, 2023
721dff6
fix: added missing semicolon in dcdc verilog
harshkhandeparkar Jun 28, 2023
6318148
fix: removed simulations from clean command
harshkhandeparkar Jun 28, 2023
2f87a09
fix: renamed dcdc-gen module_name to prevent collision
harshkhandeparkar Jun 28, 2023
f9adecc
fix<dcdc>: run make finish for synth and apr
harshkhandeparkar Jul 1, 2023
12dde5b
fix<dcdc>: copy the correct files from flow/ to work/
harshkhandeparkar Jul 1, 2023
3bcbc7b
feat: uncomment `sky130hd_dcdc` make command
harshkhandeparkar Jul 1, 2023
13db917
feat<dcdc>: added error handling for flow steps
harshkhandeparkar Jul 1, 2023
af21bea
fix<dcdc>: added 2_1_floorplan.def as a prerequisite for the def mani…
harshkhandeparkar Jul 1, 2023
276ca01
fix<dcdc>: disabled custom macro placement which was not working
harshkhandeparkar Jul 8, 2023
de601d5
fix<dcdc>: disabled the noise injection module
harshkhandeparkar Jul 8, 2023
633203a
fix<dcdc>: commented unused input
harshkhandeparkar Jul 11, 2023
567747b
fix<dcdc>: updated design name for sky130hs
harshkhandeparkar Jul 13, 2023
b90b19b
feat<dcdc>: enabled sky130hs commands in makefile
harshkhandeparkar Jul 13, 2023
836b136
feat<dcdc>: enabled sky130hs
harshkhandeparkar Jul 13, 2023
2ac0630
fix: added the correct width values in blocks/
harshkhandeparkar Jul 22, 2023
00df85a
fix: updated more width values
harshkhandeparkar Jul 22, 2023
f7e765e
fix: removed typo from auxcell.cdl
harshkhandeparkar Jul 22, 2023
91c291c
feat: added extracted dcdc netlist
harshkhandeparkar Aug 3, 2023
1638bcc
feat: added a dcdc simulation testbench
harshkhandeparkar Aug 3, 2023
ceb1527
feat: added make command to run dcdc simulations
harshkhandeparkar Aug 3, 2023
07a978e
feat: gitignored dcdc simulations
harshkhandeparkar Aug 3, 2023
ca2b5ed
fix: removed unused code and comments in dcdc_gen.py
harshkhandeparkar Aug 3, 2023
b94e660
fix: removed unused imports in dcdc generator
harshkhandeparkar Aug 3, 2023
49ef422
fix<dcdc>: fixed typo in make clean
harshkhandeparkar Aug 3, 2023
6e04b0d
fix: uncommented flow parts in Makefile
harshkhandeparkar Jan 10, 2024
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1 change: 1 addition & 0 deletions openfasoc/generators/dcdc-gen/.gitignore
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Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
__pycache__/
work/
*.csv
simulations/runs
20 changes: 13 additions & 7 deletions openfasoc/generators/dcdc-gen/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -7,19 +7,25 @@
sky130hd_dcdc_verilog:
python3 tools/dcdc_gen.py --specfile test.json --outputDir ./work --platform sky130hd --mode verilog

sky130hd_dcdc:
python3 tools/dcdc_gen.py --specfile test.json --outputDir ./work --platform sky130hd --mode macro
python3 tools/parse_rpt.py

sky130hd_dcdc_full:
python3 tools/dcdc_gen.py --specfile test.json --outputDir ./work --platform sky130hd --mode full

# sky130hs
sky130hs_dcdc_verilog:
python3 tools/dcdc_gen.py --specfile test.json --outputDir ./work --platform sky130hs --mode verilog

# sky130hd_dcdc:
# python3 tools/dcdc_gen.py --specfile test.json --outputDir ./work --platform sky130hd --mode macro
# python3 tools/parse_rpt.py

# sky130hd_dcdc_full:
# python3 tools/dcdc_gen.py --specfile test.json --outputDir ./work --platform sky130hd --mode full
sky130hs_dcdc:
python3 tools/dcdc_gen.py --specfile test.json --outputDir ./work --platform sky130hs --mode macro
python3 tools/parse_rpt.py

clean:
rm -f error_within_x.csv golden_error_opt.csv search_result.csv
rm -rf work
rm -rf tools/*.pyc tools/__pycache__/
rm -rf flow/design/src/dcdc
rm -rf simulations/runs
cd flow && make nuke
cd simulations && rm -rf run
12 changes: 6 additions & 6 deletions openfasoc/generators/dcdc-gen/blocks/sky130hd/spice/auxcell.cdl
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Expand Up @@ -17,10 +17,10 @@ X10 VMN CLK VPWR VPWR sky130_fd_pr__pfet_01v8 w=420000u l=150000u m=2
.subckt DCDC_XSW_PMOS VPB clk clkb vIN vOUT0 vOUT1
x0 int_sw0 int_sw1 vIN VPB sky130_fd_pr__pfet_01v8 w=420000u l=150000u m=2
x1 int_sw1 int_sw0 vIN VPB sky130_fd_pr__pfet_01v8 w=420000u l=150000u m=2
x2 vOUT0 int_sw0 vIN VPB sky130_fd_pr__pfet_01v8 w=1260e-9 l=150000u m=2
x3 vOUT1 int_sw1 vIN VPB sky130_fd_pr__pfet_01v8 w=1260e-9 l=150000u m=2
x4 clkb int_sw0 clkb clkb sky130_fd_pr__pfet_01v8 w=210000u l=210000u m=2
x5 clk int_sw1 clk clk sky130_fd_pr__pfet_01v8 w=210000u l=210000u m=2
x2 vOUT0 int_sw0 vIN VPB sky130_fd_pr__pfet_01v8 w=840000u l=150000u m=2
x3 vOUT1 int_sw1 vIN VPB sky130_fd_pr__pfet_01v8 w=840000u l=150000u m=2
x4 clkb int_sw0 clkb clkb sky130_fd_pr__pfet_01v8 w=420000u l=210000u m=2
x5 clk int_sw1 clk clk sky130_fd_pr__pfet_01v8 w=420000u l=210000u m=2
.ends DCDC_XSW_PMOS

* 2:1 stage: NMOS SWITCH
Expand All @@ -29,8 +29,8 @@ x0 int_sw0 int_sw1 vIN VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u m=2
x1 int_sw1 int_sw0 vIN VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u m=2
x2 vOUT0 int_sw0 vIN VNB sky130_fd_pr__nfet_01v8 w=840000u l=150000u m=2
x3 vOUT1 int_sw1 vIN VNB sky130_fd_pr__nfet_01v8 w=840000u l=150000u m=2
x4 clkb int_sw0 clkb clkb sky130_fd_pr__pfet_01v8 w=210000u l=210000u m=2
x5 clk int_sw1 clk clk sky130_fd_pr__pfet_01v8 w=210000u l=210000u m=2
x4 clkb int_sw0 clkb clkb sky130_fd_pr__pfet_01v8 w=420000u l=210000u m=2
x5 clk int_sw1 clk clk sky130_fd_pr__pfet_01v8 w=420000u l=210000u m=2
.ends DCDC_XSW_NMOS

*2:1 converter: DCDC_HUNIT_CONV2to1
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12 changes: 6 additions & 6 deletions openfasoc/generators/dcdc-gen/blocks/sky130hs/spice/auxcell.cdl
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Expand Up @@ -17,10 +17,10 @@ X10 VMN CLK VPWR VPWR sky130_fd_pr__pfet_01v8 w=420000u l=150000u m=2
.subckt DCDC_XSW_PMOS VPB clk clkb vIN vOUT0 vOUT1
x0 int_sw0 int_sw1 vIN VPB sky130_fd_pr__pfet_01v8 w=420000u l=150000u m=2
x1 int_sw1 int_sw0 vIN VPB sky130_fd_pr__pfet_01v8 w=420000u l=150000u m=2
x2 vOUT0 int_sw0 vIN VPB sky130_fd_pr__pfet_01v8 w=1260e-9 l=150000u m=2
x3 vOUT1 int_sw1 vIN VPB sky130_fd_pr__pfet_01v8 w=1260e-9 l=150000u m=2
x4 clkb int_sw0 clkb clkb sky130_fd_pr__pfet_01v8 w=210000u l=210000u m=2
x5 clk int_sw1 clk clk sky130_fd_pr__pfet_01v8 w=210000u l=210000u m=2
x2 vOUT0 int_sw0 vIN VPB sky130_fd_pr__pfet_01v8 w=840000u l=150000u m=2
x3 vOUT1 int_sw1 vIN VPB sky130_fd_pr__pfet_01v8 w=840000u l=150000u m=2
x4 clkb int_sw0 clkb clkb sky130_fd_pr__pfet_01v8 w=420000u l=210000u m=2
x5 clk int_sw1 clk clk sky130_fd_pr__pfet_01v8 w=420000u l=210000u m=2
.ends DCDC_XSW_PMOS

* 2:1 stage: NMOS SWITCH
Expand All @@ -29,8 +29,8 @@ x0 int_sw0 int_sw1 vIN VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u m=2
x1 int_sw1 int_sw0 vIN VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u m=2
x2 vOUT0 int_sw0 vIN VNB sky130_fd_pr__nfet_01v8 w=840000u l=150000u m=2
x3 vOUT1 int_sw1 vIN VNB sky130_fd_pr__nfet_01v8 w=840000u l=150000u m=2
x4 clkb int_sw0 clkb clkb sky130_fd_pr__pfet_01v8 w=210000u l=210000u m=2
x5 clk int_sw1 clk clk sky130_fd_pr__pfet_01v8 w=210000u l=210000u m=2
x4 clkb int_sw0 clkb clkb sky130_fd_pr__pfet_01v8 w=420000u l=210000u m=2
x5 clk int_sw1 clk clk sky130_fd_pr__pfet_01v8 w=420000u l=210000u m=2
.ends DCDC_XSW_NMOS

*2:1 converter: DCDC_HUNIT_CONV2to1
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4 changes: 2 additions & 2 deletions openfasoc/generators/dcdc-gen/flow/Makefile
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What is the reason for removing dependencies for macro placement?

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Neither the macro placement nor the place_six_stage.py file were working. I believe the Python file is incomplete, and the macro placement has some outdated code and no longer works with the latest version of OpenROAD. I had removed them to test if the rest of the flow was working, but it was not. Should I revert these changes?

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@minghungumich ?

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@andylithia can you review this PR.

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Can you revert the changes and submit an issue about the dependency issue you're seeing? I can try to fix it

Original file line number Diff line number Diff line change
Expand Up @@ -13,8 +13,8 @@ default: finish
# ==============================================================================

# Include design and platform configuration

DESIGN_CONFIG = ./design/sky130hd/dcdc/config.mk
PLATFORM_ARG ?= sky130hd
DESIGN_CONFIG = ./design/$(PLATFORM_ARG)/dcdc/config.mk

include $(DESIGN_CONFIG)

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2 changes: 1 addition & 1 deletion openfasoc/generators/dcdc-gen/flow/design/sky130hd/dcdc/config.mk
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@@ -1,5 +1,5 @@
export DESIGN_NICKNAME = dcdc
export DESIGN_NAME = DCDC_SIX_STAGES_CONV
export DESIGN_NAME = DCDC_CONV

export PLATFORM = sky130hd
#export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
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2 changes: 1 addition & 1 deletion openfasoc/generators/dcdc-gen/flow/design/sky130hs/dcdc/config.mk
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@@ -1,5 +1,5 @@
export DESIGN_NICKNAME = dcdc
export DESIGN_NAME = DCDC_SIX_STAGES_CONV
export DESIGN_NAME = DCDC_CONV

export PLATFORM = sky130hs
#export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
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1 change: 1 addition & 0 deletions openfasoc/generators/dcdc-gen/flow/design/src/.gitignore
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@@ -0,0 +1 @@
dcdc/
21 changes: 0 additions & 21 deletions openfasoc/generators/dcdc-gen/flow/design/src/dcdc/DCDC_BUFFER.sv
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This file was deleted.

73 changes: 0 additions & 73 deletions openfasoc/generators/dcdc-gen/flow/design/src/dcdc/DCDC_NOV_CLKGEN.sv
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32 changes: 0 additions & 32 deletions openfasoc/generators/dcdc-gen/flow/design/src/dcdc/DCDC_POWMUX.v
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83 changes: 0 additions & 83 deletions openfasoc/generators/dcdc-gen/flow/design/src/dcdc/DCDC_SIX_STAGES_CONV.v
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