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@RobertGlein
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@alessandrothea
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Hi Robert,

Thanks for the pull request.
I'm, not familiar with block designs, could you point to some documentation to educate myself?
Is there an example firmware project using block designs I can test your ipbb changes on?

Thanks!

@RobertGlein
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Hi Alessandro,

Here is the Xilinx documentation: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug994-vivado-ip-subsystems.pdf

Example project 1: You can use "Open Example Project" in the quick start tile of Vivado 2018.2 and select the "Configurable MicroBlaze Design".

Example project 2: I added you to my GitLab project using the ipbb: https://gitlab.cern.ch/rglein/fpga

Best

@RobertGlein
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W.r.t. example project 2:
You may want to look at the .gitlab-ci.yml to build it or just look at the CI/CD logs.
I also had to adjust the ipbb/cli/repo.py to enable git repos from folders: https://github.com/RobertGlein/ipbb/blob/master/ipbb/cli/repo.py

@alessandrothea
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Sorry for not having come back to you for so long. I haven't been able to review the code in detail yet (or to work on ipbb lately), but I see that the pull request branch is evolving beyond the point of the pull request itself. IF this is the case it's likely that I'll have to reject it.

@RobertGlein
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Our fork is evolving and we added reasonable features such as Vivado simulation. Feel free to reject it but maybe it will benefit your build tool. Here are the links to some documentation if you are interested:
https://gitlab.cern.ch/rglein/fpga/blob/master/framework/doc/build_framework.txt
https://gitlab.cern.ch/rglein/fpga/blob/master/framework/doc/vivado_simulation.txt

@alessandrothea
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Sure, I don't argue with that, but the purpose of pull requests is controlled inclusion of new features.
So I would have expected pull request to come from a semi-frozen branch, while it looks it's hooked on your master which is rightfully evolving,

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2 participants