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Add N_SLV_<slave name>_ADDR_WIDTH constants. #305

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Add N_SLV_<slave name>_ADDR_WIDTH constants. #305

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44a7f1f
Add N_SLV_<slave name>_ADDR_WIDTH constants.
damib Aug 29, 2023
ff49ad1
Merge branch 'master' into master
damib Sep 2, 2023
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9 changes: 5 additions & 4 deletions uhal/tools/scripts/gen_ipbus_addr_decode
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
#!/usr/bin/env python
#!/usr/libexec/platform-python

"""
This script automatically generates address select logic for IPbus-based firmware designs.
Expand Down Expand Up @@ -296,7 +296,7 @@ def main():
error_count += 1
or_prod = or_prod | (addr_bits & ~mask_bits)
and_prod = and_prod & (addr_bits | mask_bits)
slaves.append((n, i.name, addr_bits, mask_bits))
slaves.append((n, i.name, addr_bits, mask_bits, i.width))

addr_mask = or_prod & ~and_prod
log.info("Significant address bits 0b%s" % str(addr_mask))
Expand All @@ -322,9 +322,10 @@ def main():
snippet1 = "-- START automatically generated VHDL" + timestamp_suffix + "\n"
if numSlaves > 0:
slaveIds={}
for n,id,addr_bits,mask_bits in slaves:
for n,id,addr_bits,mask_bits,width in slaves:
slaveIds[n]="N_SLV_"+id.upper().replace(".","_")
snippet1 += " constant "+slaveIds[n]+": integer := %i;\n"%n
snippet1 += " constant "+slaveIds[n]+"_ADDR_WIDTH: integer := %i;\n"%width
snippet1 += " constant N_SLAVES: integer := %i;\n"%(numSlaves)
snippet1 += "-- END automatically generated VHDL"

Expand All @@ -335,7 +336,7 @@ def main():
elif numSlaves == 1:
snippet2 += " sel := ipbus_sel_t(to_unsigned(" + slaveIds[0] + ", IPBUS_SEL_WIDTH));\n"
else:
for n,id,addr_bits,mask_bits in slaves:
for n,id,addr_bits,mask_bits,width in slaves:
mask = addr_mask & ~mask_bits
if n == 0:
snippet2 += " if "
Expand Down