Enable Triple Buffered GEMM

[adedespirlet]

This PR :

• includes a working example of a Triple Buffered GEMM in Wave (tests/kernel/wave_gemm_test.py) using manual scheduling.
• includes updated documentation in wave_schedule_2.py explaining the pipelining mechanics.
• fixes a bug in loop_reconstruction.py where the buffer rotation logic during the kernel to epilogue transition worked for 2 stage pipelines but was incorrect for pipelines deeper than 2.

Note: I currently do not have access to the target hardware to verify correctness so I am testing it here with CI

Implementation Details
Instead of introducing an explicit multi_buffer_count argument, this PR leverages the existing scheduling infrastructure to achieve triple buffering natively.
By inserting an empty pipeline stage between the global loads and the compute stage, we increase the pipeline depth without increasing the initiation interval. This effectively extends the lifetime of the loaded data across an extra iteration, which compels the compiler's buffer analysis to allocate a 3rd buffer to prevent hazards. This approach was preferred as it aligns with the current stage centric loop construction logic, avoiding big changes required to support an explicit buffer count parameter.

loop_reconstruction.py BUG and FIX:
After the kernel yields its final iteration, the buffer list has been rotated. When the epilogue tries to extract these buffers it gets them in the rotated order. The original code then didn't account for this rotation, causing a mismatch. Solution: Applied a -1 rotation to compensate for how the buffers were organized when yielded, so the epilogue reads them in the correct order.

Next
Add logic to verify that the pipeline stages defined in the schedule do not exceed the device's shared memory capacity
Add lit_test

[panditsa]

Do you mind also adding a standalone example, either under 6.2_schedule.py or 6.3_schedule.py?

[panditsa]

LGTM