FIRRTL version 5.1.0
circuit top:
option Platform:
FPGA
module DefaultTarget:
input reset: Reset
module FPGATarget:
input reset: Reset
public module top:
input clk: Clock
input reset: UInt<1>
instchoice proc of DefaultTarget, Platform:
FPGA => FPGATarget
connect proc.reset, reset$ firtool foo.fir -o /dev/null
$ firtool foo.fir --select-default-for-unspecified-instance-choice -o /dev/null
foo.fir:10:11: error: a port "reset" with abstract reset type was unable to be inferred by InferResets (is this a top-level port?)
input reset: Reset
^
foo.fir:9:3: note: the module with this uninferred reset port was defined here
module FPGATarget:
