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Pull requests: llvm/circt
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[LLHD] Preserve explicit register initializers through Deseq
#11081
opened Sep 5, 2026 by
5iri
Contributor
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[ProbeToSV] Lower probe.send/probe.read to SV
#11077
opened Sep 3, 2026 by
nanjo712
Contributor
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[Arc] Lower local LLHD signals to model state
#11073
opened Sep 2, 2026 by
hovhannes-96
Contributor
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[FIRRTL] Handle forceable registers in comb loop analysis
#11070
opened Sep 1, 2026 by
prithayan
Contributor
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[FIRRTL] Preserve register initial values in optimizer
#11069
opened Sep 1, 2026 by
prithayan
Contributor
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[ImportVerilog] Emit labeled concurrent assertions outside a procedure
#11065
opened Aug 30, 2026 by
zarubaf
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[AXI4] Add concurrent read/write count to subordinate-like ops
#11062
opened Aug 28, 2026 by
TaoBi22
Contributor
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[Moore] Add missing conversions to open array typesAdd support for OpenUnpackedArrayType constants
#11058
opened Aug 27, 2026 by
ayush213
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[FIRRTL] Warn on abstract resets on extmodule's.
#11055
opened Aug 26, 2026 by
dtzSiFive
Contributor
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[MLIR] Update SymbolTable::getVisibilityAttrName callers to SymbolOpInterface::getDefaultVisibilityAttrName
#11053
opened Aug 26, 2026 by
ethansaurusrex
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[AXI4] Add verify-axi4-networks pass
#11052
opened Aug 26, 2026 by
TaoBi22
Contributor
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7/7
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[ImportVerilog] Support enum next, prev, name methods
ImportVerilog
#11042
opened Aug 21, 2026 by
fabianschuiki
Contributor
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[datapath] Lower Product of Sum to a Booth Encoded Partial Product Array
#11039
opened Aug 21, 2026 by
cowardsa
Contributor
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[OM] Avoid full module verification in release builds
#11037
opened Aug 20, 2026 by
uenoku
Member
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[ImportVerilog] Fix lvalue conversion for output/inout/ref arguments
ImportVerilog
#11033
opened Aug 19, 2026 by
fabianschuiki
Contributor
•
3/3
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[LLHD][Mem2Reg] Finer-grained promotion slots
#11018
opened Aug 18, 2026 by
AlviseDeFaveri
Contributor
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[HW][Sim] Add SimulationVariableTypeInterface to let
hw.inout hold sim value types
#10997
opened Aug 15, 2026 by
okekayode
Contributor
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[Sim] Add Involving the Sim dialect or other simulation concerns
sim.assoc_array.clear op
Simulator
#10996
opened Aug 15, 2026 by
okekayode
Contributor
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[ImportVerilog] Save the source text of the assert/assume/cover statements.
#10990
opened Aug 14, 2026 by
hovhannes-96
Contributor
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[HW] Support struct_inject, struct_explode, and single-field struct_create in HWAggregateToComb
#10981
opened Aug 12, 2026 by
jpienaar
Member
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What’s not been updated in a month: updated:<2026-08-05.