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[ImportVerilog] Streaming operators fail on unpacked arrays #11028

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@fabianschuiki

Streaming concatenation operators ({>>{...}}, {<<{...}}) need to convert non-packed, fixed-size aggregates (unpacked arrays, unpacked structs) to and from a flat packed bit vector, and ImportVerilog has no such conversion, so any streaming operand that isn't already a plain packed type fails to import. This bug used to be hidden by the moore.conversion op that pretended to convert an unpacked array to a dense bit vector. That op no longer exists after #11024.

module Streaming;
  logic [15:0] vec_3;
  logic [31:0] vec_1;
  logic arr_1 [63:0];

  initial begin
    vec_1 = {<<byte{vec_3, arr_1 with [15:0]}};
    {<<byte{vec_3, arr_1 with [15:0]}} = vec_1;
  end
endmodule
error: unsupported conversion from '!moore.uarray<16 x l1>' to '!moore.l16'

Per IEEE 1800-2017 §11.4.14, streaming braces accept packed types, strings, unpacked arrays (fixed-size, dynamic, and queues), unpacked structs/unions, and class handles (source-only); with [..] part-select is further restricted to fixed-size unpacked arrays, dynamic arrays, and queues.

Context::materializeConversion in ImportVerilog needs a conversion path for fixed-size aggregates, gated on both sides having equal, statically-known UnpackedType::getBitSize(). moore.conversion's existing MooreToCore lowering already does a width-checked bitcast for such pairs, so this is mostly a frontend-side gap. Queues, dynamic arrays, and associative arrays should stay unsupported since they have no static width to bitcast against.

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