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AMDGPU: Directly select minimumnum/maximumnum with ieee_mode=0
The hardware min/max follow the IR rules with IEEE mode disabled, so we can avoid the canonicalizes of the input. We lose the quieting of a signaling nan if both inputs are nans, but we only require that with strictfp.
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9 files changed

+1365
-1673
lines changed

9 files changed

+1365
-1673
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,8 @@ def FP64Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().F
9292
def NoFP16Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals == DenormalMode::getPreserveSign()">;
9393
def NoFP32Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().FP32Denormals == DenormalMode::getPreserveSign()">;
9494
def NoFP64Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals == DenormalMode::getPreserveSign()">;
95+
def IEEEModeEnabled : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().IEEE">;
96+
def IEEEModeDisabled : Predicate<"!MF->getInfo<SIMachineFunctionInfo>()->getMode().IEEE">;
9597
def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
9698
}
9799

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 15 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -957,12 +957,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
957957
FPOpActions.clampMaxNumElementsStrict(0, S32, 2);
958958
}
959959

960-
auto &MinNumMaxNum = getActionDefinitionsBuilder({
961-
G_FMINNUM, G_FMAXNUM, G_FMINNUM_IEEE, G_FMAXNUM_IEEE});
962-
963-
// TODO: These should be custom lowered and are directly legal with IEEE=0
964-
auto &MinimumNumMaximumNum =
965-
getActionDefinitionsBuilder({G_FMINIMUMNUM, G_FMAXIMUMNUM});
960+
auto &MinNumMaxNum = getActionDefinitionsBuilder(
961+
{G_FMINNUM, G_FMAXNUM, G_FMINIMUMNUM, G_FMAXIMUMNUM, G_FMINNUM_IEEE,
962+
G_FMAXNUM_IEEE});
966963

967964
if (ST.hasVOP3PInsts()) {
968965
MinNumMaxNum.customFor(FPTypesPK16)
@@ -980,8 +977,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
980977
.scalarize(0);
981978
}
982979

983-
MinimumNumMaximumNum.lower();
984-
985980
if (ST.hasVOP3PInsts())
986981
FPOpActions.clampMaxNumElementsStrict(0, S16, 2);
987982

@@ -2160,6 +2155,8 @@ bool AMDGPULegalizerInfo::legalizeCustom(
21602155
return legalizeFPTOI(MI, MRI, B, false);
21612156
case TargetOpcode::G_FMINNUM:
21622157
case TargetOpcode::G_FMAXNUM:
2158+
case TargetOpcode::G_FMINIMUMNUM:
2159+
case TargetOpcode::G_FMAXIMUMNUM:
21632160
case TargetOpcode::G_FMINNUM_IEEE:
21642161
case TargetOpcode::G_FMAXNUM_IEEE:
21652162
return legalizeMinNumMaxNum(Helper, MI);
@@ -2739,9 +2736,17 @@ bool AMDGPULegalizerInfo::legalizeMinNumMaxNum(LegalizerHelper &Helper,
27392736
MI.getOpcode() == AMDGPU::G_FMAXNUM_IEEE;
27402737

27412738
// With ieee_mode disabled, the instructions have the correct behavior
2742-
// already for G_FMINNUM/G_FMAXNUM
2743-
if (!MFI->getMode().IEEE)
2739+
// already for G_FMINIMUMNUM/G_FMAXIMUMNUM.
2740+
//
2741+
// FIXME: G_FMINNUM/G_FMAXNUM should match the behavior with ieee_mode
2742+
// enabled.
2743+
if (!MFI->getMode().IEEE) {
2744+
if (MI.getOpcode() == AMDGPU::G_FMINIMUMNUM ||
2745+
MI.getOpcode() == AMDGPU::G_FMAXIMUMNUM)
2746+
return true;
2747+
27442748
return !IsIEEEOp;
2749+
}
27452750

27462751
if (IsIEEEOp)
27472752
return true;

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4009,6 +4009,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
40094009
case AMDGPU::G_FMAXNUM:
40104010
case AMDGPU::G_FMINIMUM:
40114011
case AMDGPU::G_FMAXIMUM:
4012+
case AMDGPU::G_FMINIMUMNUM:
4013+
case AMDGPU::G_FMAXIMUMNUM:
40124014
case AMDGPU::G_INTRINSIC_TRUNC:
40134015
case AMDGPU::G_STRICT_FADD:
40144016
case AMDGPU::G_STRICT_FSUB:

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 29 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -523,8 +523,9 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
523523
setOperationAction({ISD::SADDSAT, ISD::SSUBSAT}, {MVT::i16, MVT::i32},
524524
Legal);
525525

526-
setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, {MVT::f32, MVT::f64},
527-
Custom);
526+
setOperationAction(
527+
{ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
528+
{MVT::f32, MVT::f64}, Custom);
528529

529530
// These are really only legal for ieee_mode functions. We should be avoiding
530531
// them for functions that don't have ieee_mode enabled, so just say they are
@@ -756,7 +757,9 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
756757
// allows matching fneg (fabs x) patterns)
757758
setOperationAction(ISD::FABS, MVT::v2f16, Legal);
758759

759-
setOperationAction({ISD::FMAXNUM, ISD::FMINNUM}, MVT::f16, Custom);
760+
setOperationAction(
761+
{ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
762+
MVT::f16, Custom);
760763
setOperationAction({ISD::FMAXNUM_IEEE, ISD::FMINNUM_IEEE}, MVT::f16, Legal);
761764

762765
setOperationAction({ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE, ISD::FMINIMUMNUM,
@@ -810,8 +813,9 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
810813
setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FCANONICALIZE},
811814
VT, Custom);
812815

813-
setOperationAction({ISD::FMAXNUM, ISD::FMINNUM}, {MVT::v2f16, MVT::v4f16},
814-
Custom);
816+
setOperationAction(
817+
{ISD::FMAXNUM, ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM},
818+
{MVT::v2f16, MVT::v4f16}, Custom);
815819

816820
setOperationAction(ISD::FEXP, MVT::v2f16, Custom);
817821
setOperationAction(ISD::SELECT, {MVT::v4i16, MVT::v4f16, MVT::v4bf16},
@@ -6057,6 +6061,9 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
60576061
case ISD::FMINNUM:
60586062
case ISD::FMAXNUM:
60596063
return lowerFMINNUM_FMAXNUM(Op, DAG);
6064+
case ISD::FMINIMUMNUM:
6065+
case ISD::FMAXIMUMNUM:
6066+
return lowerFMINIMUMNUM_FMAXIMUMNUM(Op, DAG);
60606067
case ISD::FMINIMUM:
60616068
case ISD::FMAXIMUM:
60626069
return lowerFMINIMUM_FMAXIMUM(Op, DAG);
@@ -6081,8 +6088,6 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
60816088
case ISD::FMUL:
60826089
case ISD::FMINNUM_IEEE:
60836090
case ISD::FMAXNUM_IEEE:
6084-
case ISD::FMINIMUMNUM:
6085-
case ISD::FMAXIMUMNUM:
60866091
case ISD::UADDSAT:
60876092
case ISD::USUBSAT:
60886093
case ISD::SADDSAT:
@@ -6967,6 +6972,23 @@ SDValue SITargetLowering::lowerFMINNUM_FMAXNUM(SDValue Op,
69676972
return Op;
69686973
}
69696974

6975+
SDValue
6976+
SITargetLowering::lowerFMINIMUMNUM_FMAXIMUMNUM(SDValue Op,
6977+
SelectionDAG &DAG) const {
6978+
EVT VT = Op.getValueType();
6979+
const MachineFunction &MF = DAG.getMachineFunction();
6980+
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
6981+
bool IsIEEEMode = Info->getMode().IEEE;
6982+
6983+
if (IsIEEEMode)
6984+
return expandFMINIMUMNUM_FMAXIMUMNUM(Op.getNode(), DAG);
6985+
6986+
if (VT == MVT::v4f16 || VT == MVT::v8f16 || VT == MVT::v16f16 ||
6987+
VT == MVT::v16bf16)
6988+
return splitBinaryVectorOp(Op, DAG);
6989+
return Op;
6990+
}
6991+
69706992
SDValue SITargetLowering::lowerFMINIMUM_FMAXIMUM(SDValue Op,
69716993
SelectionDAG &DAG) const {
69726994
EVT VT = Op.getValueType();

‎llvm/lib/Target/AMDGPU/SIISelLowering.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -146,6 +146,7 @@ class SITargetLowering final : public AMDGPUTargetLowering {
146146
/// Custom lowering for ISD::FP_ROUND for MVT::f16.
147147
SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
148148
SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
149+
SDValue lowerFMINIMUMNUM_FMAXIMUMNUM(SDValue Op, SelectionDAG &DAG) const;
149150
SDValue lowerFMINIMUM_FMAXIMUM(SDValue Op, SelectionDAG &DAG) const;
150151
SDValue lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const;
151152
SDValue promoteUniformOpToI32(SDValue Op, DAGCombinerInfo &DCI) const;

‎llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1376,6 +1376,52 @@ def : GCNPat <
13761376
(i32 (V_MOV_B32_e32 (i32 0))), sub1)
13771377
>;
13781378

1379+
1380+
1381+
class FPBinOpPat <SDPatternOperator node, ValueType vt, Instruction inst>
1382+
: GCNPat <(vt (node (vt (VOP3Mods vt:$src0, i32:$src0_mods)),
1383+
(vt (VOP3Mods vt:$src1, i32:$src1_mods)))),
1384+
(inst $src0_mods, $src0, $src1_mods, $src1, DSTCLAMP.NONE, DSTOMOD.NONE)
1385+
>;
1386+
1387+
class FPPkBinOpPat <SDPatternOperator node, ValueType vt, Instruction inst>
1388+
: GCNPat <(vt (node (VOP3PMods v2f16:$src0, i32:$src0_mods),
1389+
(VOP3PMods v2f16:$src1, i32:$src1_mods))),
1390+
(inst $src0_mods, $src0, $src1_mods, $src1, DSTCLAMP.NONE)
1391+
>;
1392+
1393+
/// With IEEE=0, signalingness is ignored and the non-nan input will
1394+
/// be directly returned.
1395+
let OtherPredicates = [IEEEModeDisabled] in {
1396+
def : FPBinOpPat<fminimumnum, f32, V_MIN_F32_e64>;
1397+
def : FPBinOpPat<fmaximumnum, f32, V_MAX_F32_e64>;
1398+
def : FPBinOpPat<fminimumnum, f64, V_MIN_F64_e64>;
1399+
def : FPBinOpPat<fmaximumnum, f64, V_MAX_F64_e64>;
1400+
1401+
let SubtargetPredicate = Has16BitInsts,
1402+
True16Predicate = NotHasTrue16BitInsts in {
1403+
def : FPBinOpPat<fminimumnum, f16, V_MIN_F16_e64>;
1404+
def : FPBinOpPat<fmaximumnum, f16, V_MAX_F16_e64>;
1405+
}
1406+
1407+
let SubtargetPredicate = Has16BitInsts,
1408+
True16Predicate = UseRealTrue16Insts in {
1409+
def : FPBinOpPat<fminimumnum, f16, V_MIN_F16_t16_e64>;
1410+
def : FPBinOpPat<fmaximumnum, f16, V_MAX_F16_t16_e64>;
1411+
}
1412+
1413+
let SubtargetPredicate = Has16BitInsts,
1414+
True16Predicate = UseFakeTrue16Insts in {
1415+
def : FPBinOpPat<fminimumnum, f16, V_MIN_F16_fake16_e64>;
1416+
def : FPBinOpPat<fmaximumnum, f16, V_MAX_F16_fake16_e64>;
1417+
}
1418+
1419+
let SubtargetPredicate = HasVOP3PInsts in {
1420+
def : FPPkBinOpPat<fminimumnum, v2f16, V_PK_MIN_F16>;
1421+
def : FPPkBinOpPat<fmaximumnum, v2f16, V_PK_MAX_F16>;
1422+
}
1423+
}
1424+
13791425
/********** ============================================ **********/
13801426
/********** Extraction, Insertion, Building and Casting **********/
13811427
/********** ============================================ **********/

‎llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll

Lines changed: 12 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -2019,9 +2019,7 @@ define float @v_fneg_minimumnum_f32_no_ieee(float %a, float %b) #4 {
20192019
; GCN-LABEL: v_fneg_minimumnum_f32_no_ieee:
20202020
; GCN: ; %bb.0:
20212021
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2022-
; GCN-NEXT: v_mul_f32_e32 v1, -1.0, v1
2023-
; GCN-NEXT: v_mul_f32_e32 v0, -1.0, v0
2024-
; GCN-NEXT: v_max_f32_e32 v0, v0, v1
2022+
; GCN-NEXT: v_max_f32_e64 v0, -v0, -v1
20252023
; GCN-NEXT: s_setpc_b64 s[30:31]
20262024
%min = call float @llvm.minimumnum.f32(float %a, float %b)
20272025
%fneg = fneg float %min
@@ -2044,8 +2042,7 @@ define float @v_fneg_self_minimumnum_f32_no_ieee(float %a) #4 {
20442042
; GCN-LABEL: v_fneg_self_minimumnum_f32_no_ieee:
20452043
; GCN: ; %bb.0:
20462044
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2047-
; GCN-NEXT: v_mul_f32_e32 v0, -1.0, v0
2048-
; GCN-NEXT: v_max_f32_e32 v0, v0, v0
2045+
; GCN-NEXT: v_max_f32_e64 v0, -v0, -v0
20492046
; GCN-NEXT: s_setpc_b64 s[30:31]
20502047
%min = call float @llvm.minimumnum.f32(float %a, float %a)
20512048
%min.fneg = fneg float %min
@@ -2068,8 +2065,7 @@ define float @v_fneg_posk_minimumnum_f32_no_ieee(float %a) #4 {
20682065
; GCN-LABEL: v_fneg_posk_minimumnum_f32_no_ieee:
20692066
; GCN: ; %bb.0:
20702067
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2071-
; GCN-NEXT: v_mul_f32_e32 v0, -1.0, v0
2072-
; GCN-NEXT: v_max_f32_e32 v0, -4.0, v0
2068+
; GCN-NEXT: v_max_f32_e64 v0, -v0, -4.0
20732069
; GCN-NEXT: s_setpc_b64 s[30:31]
20742070
%min = call float @llvm.minimumnum.f32(float 4.0, float %a)
20752071
%fneg = fneg float %min
@@ -2092,8 +2088,7 @@ define float @v_fneg_negk_minimumnum_f32_no_ieee(float %a) #4 {
20922088
; GCN-LABEL: v_fneg_negk_minimumnum_f32_no_ieee:
20932089
; GCN: ; %bb.0:
20942090
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2095-
; GCN-NEXT: v_mul_f32_e32 v0, -1.0, v0
2096-
; GCN-NEXT: v_max_f32_e32 v0, 4.0, v0
2091+
; GCN-NEXT: v_max_f32_e64 v0, -v0, 4.0
20972092
; GCN-NEXT: s_setpc_b64 s[30:31]
20982093
%min = call float @llvm.minimumnum.f32(float -4.0, float %a)
20992094
%fneg = fneg float %min
@@ -2251,8 +2246,7 @@ define float @v_fneg_neg0_minimumnum_f32_no_ieee(float %a) #4 {
22512246
; GCN-LABEL: v_fneg_neg0_minimumnum_f32_no_ieee:
22522247
; GCN: ; %bb.0:
22532248
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2254-
; GCN-NEXT: v_mul_f32_e32 v0, -1.0, v0
2255-
; GCN-NEXT: v_max_f32_e32 v0, 0, v0
2249+
; GCN-NEXT: v_max_f32_e64 v0, -v0, 0
22562250
; GCN-NEXT: s_setpc_b64 s[30:31]
22572251
%min = call float @llvm.minimumnum.f32(float -0.0, float %a)
22582252
%fneg = fneg float %min
@@ -2299,7 +2293,6 @@ define float @v_fneg_0_minimumnum_foldable_use_f32_no_ieee(float %a, float %b) #
22992293
; GCN-LABEL: v_fneg_0_minimumnum_foldable_use_f32_no_ieee:
23002294
; GCN: ; %bb.0:
23012295
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2302-
; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0
23032296
; GCN-NEXT: v_min_f32_e32 v0, 0, v0
23042297
; GCN-NEXT: v_mul_f32_e64 v0, -v0, v1
23052298
; GCN-NEXT: s_setpc_b64 s[30:31]
@@ -2330,9 +2323,7 @@ define <2 x float> @v_fneg_minimumnum_multi_use_minimumnum_f32_no_ieee(float %a,
23302323
; GCN-LABEL: v_fneg_minimumnum_multi_use_minimumnum_f32_no_ieee:
23312324
; GCN: ; %bb.0:
23322325
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2333-
; GCN-NEXT: v_mul_f32_e32 v1, -1.0, v1
2334-
; GCN-NEXT: v_mul_f32_e32 v0, -1.0, v0
2335-
; GCN-NEXT: v_max_f32_e32 v0, v0, v1
2326+
; GCN-NEXT: v_max_f32_e64 v0, -v0, -v1
23362327
; GCN-NEXT: v_mul_f32_e32 v1, -4.0, v0
23372328
; GCN-NEXT: s_setpc_b64 s[30:31]
23382329
%min = call float @llvm.minimumnum.f32(float %a, float %b)
@@ -2364,9 +2355,7 @@ define float @v_fneg_maximumnum_f32_no_ieee(float %a, float %b) #4 {
23642355
; GCN-LABEL: v_fneg_maximumnum_f32_no_ieee:
23652356
; GCN: ; %bb.0:
23662357
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2367-
; GCN-NEXT: v_mul_f32_e32 v1, -1.0, v1
2368-
; GCN-NEXT: v_mul_f32_e32 v0, -1.0, v0
2369-
; GCN-NEXT: v_min_f32_e32 v0, v0, v1
2358+
; GCN-NEXT: v_min_f32_e64 v0, -v0, -v1
23702359
; GCN-NEXT: s_setpc_b64 s[30:31]
23712360
%max = call float @llvm.maximumnum.f32(float %a, float %b)
23722361
%fneg = fneg float %max
@@ -2389,8 +2378,7 @@ define float @v_fneg_self_maximumnum_f32_no_ieee(float %a) #4 {
23892378
; GCN-LABEL: v_fneg_self_maximumnum_f32_no_ieee:
23902379
; GCN: ; %bb.0:
23912380
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2392-
; GCN-NEXT: v_mul_f32_e32 v0, -1.0, v0
2393-
; GCN-NEXT: v_min_f32_e32 v0, v0, v0
2381+
; GCN-NEXT: v_min_f32_e64 v0, -v0, -v0
23942382
; GCN-NEXT: s_setpc_b64 s[30:31]
23952383
%max = call float @llvm.maximumnum.f32(float %a, float %a)
23962384
%max.fneg = fneg float %max
@@ -2413,8 +2401,7 @@ define float @v_fneg_posk_maximumnum_f32_no_ieee(float %a) #4 {
24132401
; GCN-LABEL: v_fneg_posk_maximumnum_f32_no_ieee:
24142402
; GCN: ; %bb.0:
24152403
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2416-
; GCN-NEXT: v_mul_f32_e32 v0, -1.0, v0
2417-
; GCN-NEXT: v_min_f32_e32 v0, -4.0, v0
2404+
; GCN-NEXT: v_min_f32_e64 v0, -v0, -4.0
24182405
; GCN-NEXT: s_setpc_b64 s[30:31]
24192406
%max = call float @llvm.maximumnum.f32(float 4.0, float %a)
24202407
%fneg = fneg float %max
@@ -2437,8 +2424,7 @@ define float @v_fneg_negk_maximumnum_f32_no_ieee(float %a) #4 {
24372424
; GCN-LABEL: v_fneg_negk_maximumnum_f32_no_ieee:
24382425
; GCN: ; %bb.0:
24392426
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2440-
; GCN-NEXT: v_mul_f32_e32 v0, -1.0, v0
2441-
; GCN-NEXT: v_min_f32_e32 v0, 4.0, v0
2427+
; GCN-NEXT: v_min_f32_e64 v0, -v0, 4.0
24422428
; GCN-NEXT: s_setpc_b64 s[30:31]
24432429
%max = call float @llvm.maximumnum.f32(float -4.0, float %a)
24442430
%fneg = fneg float %max
@@ -2473,8 +2459,7 @@ define float @v_fneg_neg0_maximumnum_f32_no_ieee(float %a) #4 {
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; GCN-LABEL: v_fneg_neg0_maximumnum_f32_no_ieee:
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; GCN: ; %bb.0:
24752461
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2476-
; GCN-NEXT: v_mul_f32_e32 v0, -1.0, v0
2477-
; GCN-NEXT: v_min_f32_e32 v0, 0, v0
2462+
; GCN-NEXT: v_min_f32_e64 v0, -v0, 0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%max = call float @llvm.maximumnum.f32(float -0.0, float %a)
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%fneg = fneg float %max
@@ -2499,7 +2484,6 @@ define float @v_fneg_0_maximumnum_foldable_use_f32_no_ieee(float %a, float %b) #
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; GCN-LABEL: v_fneg_0_maximumnum_foldable_use_f32_no_ieee:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2502-
; GCN-NEXT: v_mul_f32_e32 v0, 1.0, v0
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; GCN-NEXT: v_max_f32_e32 v0, 0, v0
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; GCN-NEXT: v_mul_f32_e64 v0, -v0, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
@@ -2530,9 +2514,7 @@ define <2 x float> @v_fneg_maximumnum_multi_use_maximumnum_f32_no_ieee(float %a,
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; GCN-LABEL: v_fneg_maximumnum_multi_use_maximumnum_f32_no_ieee:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2533-
; GCN-NEXT: v_mul_f32_e32 v1, -1.0, v1
2534-
; GCN-NEXT: v_mul_f32_e32 v0, -1.0, v0
2535-
; GCN-NEXT: v_min_f32_e32 v0, v0, v1
2517+
; GCN-NEXT: v_min_f32_e64 v0, -v0, -v1
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; GCN-NEXT: v_mul_f32_e32 v1, -4.0, v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%max = call float @llvm.maximumnum.f32(float %a, float %b)

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