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[hexagon] Bump the default version to v68 (#132304)
Set the default processor version to v68 when the user does not specify one in the command line. This includes changes in the LLVM backed and linker (lld). Since lld normally sets the version based on inputs, this change will only affect cases when there are no inputs. Fixes #127558 (cherry picked from commit c0b2c10)
1 parent 90cc9ca commit d1f5a9f

20 files changed

+134
-120
lines changed

‎lld/ELF/Arch/Hexagon.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ uint32_t Hexagon::calcEFlags() const {
6868
if (!ret || eflags > *ret)
6969
ret = eflags;
7070
}
71-
return ret.value_or(/* Default Arch Rev: */ 0x60);
71+
return ret.value_or(/* Default Arch Rev: */ EF_HEXAGON_MACH_V68);
7272
}
7373

7474
static uint32_t applyMask(uint32_t mask, uint32_t data) {

‎lld/docs/ReleaseNotes.rst

+5
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,11 @@ ELF Improvements
7676
* Supported relocation types for LoongArch target: ``R_LARCH_TLS_{LD,GD,DESC}_PCREL20_S2``.
7777
(`#100105 <https://github.com/llvm/llvm-project/pull/100105>`_)
7878

79+
* The default Hexagon architecture version in ELF object files produced by
80+
lld is changed to v68. This change is only effective when the version is
81+
not provided in the command line by the user and cannot be inferred from
82+
inputs.
83+
7984
Breaking changes
8085
----------------
8186

‎lld/test/ELF/emulation-hexagon.s

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# REQUIRES: hexagon
2-
# RUN: llvm-mc -filetype=obj -triple=hexagon %s -o %t.o
2+
# RUN: llvm-mc -filetype=obj -triple=hexagon --mcpu=hexagonv73 %s -o %t.o
33
# RUN: ld.lld %t.o -o %t
44
# RUN: llvm-readelf --file-headers %t | FileCheck --check-prefix=CHECK %s
55
# RUN: ld.lld -m hexagonelf %t.o -o %t
@@ -26,7 +26,7 @@
2626
# CHECK-NEXT: Entry point address: 0x200B4
2727
# CHECK-NEXT: Start of program headers: 52 (bytes into file)
2828
# CHECK-NEXT: Start of section headers:
29-
# CHECK-NEXT: Flags: 0x60
29+
# CHECK-NEXT: Flags: 0x73
3030
# CHECK-NEXT: Size of this header: 52 (bytes)
3131
# CHECK-NEXT: Size of program headers: 32 (bytes)
3232

‎lld/test/ELF/hexagon-eflag.s

+3-2
Original file line numberDiff line numberDiff line change
@@ -3,10 +3,11 @@
33
# RUN: llvm-mc -filetype=obj -mv60 -triple=hexagon-unknown-elf %S/Inputs/hexagon.s -o %t2
44
# RUN: ld.lld %t2 %t -o %t3
55
# RUN: llvm-readelf -h %t3 | FileCheck %s
6-
# Verify that the largest arch in the input list is selected.
6+
## Verify that the largest arch in the input list is selected.
77
# CHECK: Flags: 0x62
88

9+
## Verify the arch version when it cannot be inferred from inputs.
910
# RUN: llvm-ar rcsD %t4
1011
# RUN: ld.lld -m hexagonelf %t4 -o %t5
1112
# RUN: llvm-readelf -h %t5 | FileCheck --check-prefix=CHECK-EMPTYARCHIVE %s
12-
# CHECK-EMPTYARCHIVE: Flags: 0x60
13+
# CHECK-EMPTYARCHIVE: Flags: 0x68

‎llvm/docs/ReleaseNotes.md

+4
Original file line numberDiff line numberDiff line change
@@ -202,6 +202,10 @@ Changes to the DirectX Backend
202202
Changes to the Hexagon Backend
203203
------------------------------
204204

205+
* The default Hexagon architecture version in ELF object files produced by
206+
the tools such as llvm-mc is changed to v68. This version will be set if
207+
the user does not provide the CPU version in the command line.
208+
205209
Changes to the LoongArch Backend
206210
--------------------------------
207211

‎llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@ static cl::opt<bool>
125125
static cl::opt<bool> EnableHexagonCabac
126126
("mcabac", cl::desc("tbd"), cl::init(false));
127127

128-
static StringRef DefaultArch = "hexagonv60";
128+
static constexpr StringRef DefaultArch = "hexagonv68";
129129

130130
static StringRef HexagonGetArchVariant() {
131131
if (MV5)

‎llvm/test/CodeGen/Hexagon/arg-copy-elison.ll

+11-12
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,7 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs --version 4
22
; RUN: llc -mtriple hexagon-- -o - %s | FileCheck %s
33

44
; Reproducer for https://github.com/llvm/llvm-project/issues/89060
5-
;
65
; Problem was a bug in argument copy elison. Given that the %alloca is
76
; eliminated, the same frame index will be used for accessing %alloca and %a
87
; on the fixed stack. Care must be taken when setting up
@@ -11,8 +10,15 @@
1110
; ir.alloca name), or make sure that we still detect that they alias each
1211
; other if using different kinds of MemOperands to identify the same fixed
1312
; stack entry.
14-
;
1513
define i32 @f(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 %q1, i32 %a, i32 %q2) {
14+
%alloca = alloca i32
15+
store i32 %a, ptr %alloca ; Should be elided.
16+
store i32 666, ptr %alloca
17+
%x = sub i32 %q1, %q2
18+
%y = xor i32 %x, %a ; Results in a load of %a from fixed stack.
19+
; Using same frame index as elided %alloca.
20+
ret i32 %y
21+
}
1622
; CHECK-LABEL: f:
1723
; CHECK: .cfi_startproc
1824
; CHECK-NEXT: // %bb.0:
@@ -24,16 +30,9 @@ define i32 @f(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i
2430
; CHECK-NEXT: r0 = sub(r1,r0)
2531
; CHECK-NEXT: r2 = memw(r29+#32)
2632
; CHECK-NEXT: memw(r29+#32) = ##666
27-
; CHECK-NEXT: }
33+
; CHECK-EMPTY:
34+
; CHECK-NEXT: } :mem_noshuf
2835
; CHECK-NEXT: {
2936
; CHECK-NEXT: r0 = xor(r0,r2)
3037
; CHECK-NEXT: jumpr r31
3138
; CHECK-NEXT: }
32-
%alloca = alloca i32
33-
store i32 %a, ptr %alloca ; Should be elided.
34-
store i32 666, ptr %alloca
35-
%x = sub i32 %q1, %q2
36-
%y = xor i32 %x, %a ; Results in a load of %a from fixed stack.
37-
; Using same frame index as elided %alloca.
38-
ret i32 %y
39-
}

‎llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll

+1-3
Original file line numberDiff line numberDiff line change
@@ -152,10 +152,8 @@ define i64 @atomicrmw_usub_cond_i64(ptr %ptr, i64 %val) {
152152
; CHECK-NEXT: r5:4 = memd_locked(r0)
153153
; CHECK-NEXT: }
154154
; CHECK-NEXT: {
155-
; CHECK-NEXT: r7:6 = sub(r5:4,r3:2)
156-
; CHECK-NEXT: }
157-
; CHECK-NEXT: {
158155
; CHECK-NEXT: p0 = cmp.gtu(r3:2,r5:4)
156+
; CHECK-NEXT: r7:6 = sub(r5:4,r3:2)
159157
; CHECK-NEXT: }
160158
; CHECK-NEXT: {
161159
; CHECK-NEXT: r8 = mux(p0,r4,r6)

‎llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll

+6-6
Original file line numberDiff line numberDiff line change
@@ -156,12 +156,12 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) {
156156
; CHECK-NEXT: r5:4 = memd_locked(r0)
157157
; CHECK-NEXT: }
158158
; CHECK-NEXT: {
159+
; CHECK-NEXT: p0 = cmp.gtu(r3:2,r5:4)
159160
; CHECK-NEXT: r9:8 = add(r5:4,r7:6)
160161
; CHECK-NEXT: }
161162
; CHECK-NEXT: {
162-
; CHECK-NEXT: p0 = cmp.gtu(r3:2,r5:4)
163-
; CHECK-NEXT: if (!p0.new) r8 = add(r1,#0)
164-
; CHECK-NEXT: if (!p0.new) r9 = add(r1,#0)
163+
; CHECK-NEXT: if (!p0) r8 = add(r1,#0)
164+
; CHECK-NEXT: if (!p0) r9 = add(r1,#0)
165165
; CHECK-NEXT: }
166166
; CHECK-NEXT: {
167167
; CHECK-NEXT: memd_locked(r0,p0) = r9:8
@@ -345,13 +345,13 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) {
345345
; CHECK-NEXT: r5:4 = memd_locked(r0)
346346
; CHECK-NEXT: }
347347
; CHECK-NEXT: {
348-
; CHECK-NEXT: r13:12 = add(r5:4,r7:6)
349-
; CHECK-NEXT: }
350-
; CHECK-NEXT: {
351348
; CHECK-NEXT: p1 = cmp.gtu(r5:4,r3:2)
352349
; CHECK-NEXT: p0 = cmp.eq(r5:4,r9:8)
353350
; CHECK-NEXT: }
354351
; CHECK-NEXT: {
352+
; CHECK-NEXT: r13:12 = add(r5:4,r7:6)
353+
; CHECK-NEXT: }
354+
; CHECK-NEXT: {
355355
; CHECK-NEXT: r1 = mux(p1,r2,r12)
356356
; CHECK-NEXT: r14 = mux(p1,r3,r13)
357357
; CHECK-NEXT: }

‎llvm/test/CodeGen/Hexagon/bank-conflict.mir

+1-1
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,9 @@
88
# CHECK: = A2_tfr
99
# CHECK: = L2_loadrigp
1010

11-
# CHECK: = L4_loadri_rr
1211
# CHECK: = S2_tstbit_i
1312
# CHECK: = L4_loadri_rr
13+
# CHECK: = L4_loadri_rr
1414

1515
--- |
1616
%s.0 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [3 x i32], [24 x i32], [8 x %s.1], [5 x i32] }

‎llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll

+3-2
Original file line numberDiff line numberDiff line change
@@ -12,10 +12,11 @@
1212
; The problem is that the load will execute before the store, clobbering the
1313
; pair r17:16.
1414
;
15-
; Check that the store and the load are not in the same packet.
15+
16+
; Validate that store executes before load.
1617
; CHECK: memd{{.*}} = r17:16
17-
; CHECK: }
1818
; CHECK: r17:16 = memd
19+
; CHECK: } :mem_noshuf
1920
; CHECK-LABEL: LBB0_1:
2021

2122
target triple = "hexagon"

‎llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll

+28-22
Original file line numberDiff line numberDiff line change
@@ -8,12 +8,15 @@ define i64 @f0(ptr %a0, <8 x i8> %a1) #0 {
88
; CHECK-NEXT: r0 = memub(r0+#0)
99
; CHECK-NEXT: }
1010
; CHECK-NEXT: {
11-
; CHECK-NEXT: r5:4 = combine(#0,#0)
11+
; CHECK-NEXT: r1 = #0
1212
; CHECK-NEXT: }
1313
; CHECK-NEXT: {
1414
; CHECK-NEXT: p0 = r0
1515
; CHECK-NEXT: }
1616
; CHECK-NEXT: {
17+
; CHECK-NEXT: r5:4 = vsplatb(r1)
18+
; CHECK-NEXT: }
19+
; CHECK-NEXT: {
1720
; CHECK-NEXT: r1:0 = vmux(p0,r3:2,r5:4)
1821
; CHECK-NEXT: }
1922
; CHECK-NEXT: {
@@ -114,7 +117,10 @@ define void @f4(ptr %a0, i64 %a1) #0 {
114117
; CHECK-LABEL: f4:
115118
; CHECK: // %bb.0: // %b0
116119
; CHECK-NEXT: {
117-
; CHECK-NEXT: r5:4 = combine(#0,#0)
120+
; CHECK-NEXT: r1 = #0
121+
; CHECK-NEXT: }
122+
; CHECK-NEXT: {
123+
; CHECK-NEXT: r5:4 = vsplatb(r1)
118124
; CHECK-NEXT: }
119125
; CHECK-NEXT: {
120126
; CHECK-NEXT: p0 = vcmpb.eq(r3:2,r5:4)
@@ -123,10 +129,10 @@ define void @f4(ptr %a0, i64 %a1) #0 {
123129
; CHECK-NEXT: p0 = not(p0)
124130
; CHECK-NEXT: }
125131
; CHECK-NEXT: {
126-
; CHECK-NEXT: r1 = p0
132+
; CHECK-NEXT: r2 = p0
127133
; CHECK-NEXT: }
128134
; CHECK-NEXT: {
129-
; CHECK-NEXT: memb(r0+#0) = r1
135+
; CHECK-NEXT: memb(r0+#0) = r2
130136
; CHECK-NEXT: }
131137
; CHECK-NEXT: {
132138
; CHECK-NEXT: jumpr r31
@@ -173,64 +179,64 @@ define void @f6(ptr %a0, i16 %a1) #0 {
173179
; CHECK-LABEL: f6:
174180
; CHECK: // %bb.0: // %b0
175181
; CHECK-NEXT: {
176-
; CHECK-NEXT: r2 = extractu(r1,#8,#8)
182+
; CHECK-NEXT: r2 = #255
177183
; CHECK-NEXT: }
178184
; CHECK-NEXT: {
179-
; CHECK-NEXT: r3 = #255
185+
; CHECK-NEXT: r3 = extractu(r1,#8,#8)
180186
; CHECK-NEXT: }
181187
; CHECK-NEXT: {
182-
; CHECK-NEXT: p1 = !bitsclr(r1,r3)
188+
; CHECK-NEXT: p1 = !bitsclr(r1,r2)
183189
; CHECK-NEXT: }
184190
; CHECK-NEXT: {
185-
; CHECK-NEXT: p0 = cmp.eq(r2,#0)
191+
; CHECK-NEXT: p0 = cmp.eq(r3,#0)
186192
; CHECK-NEXT: }
187193
; CHECK-NEXT: {
188-
; CHECK-NEXT: if (p0) r2 = #0
194+
; CHECK-NEXT: if (p0) r3 = #0
189195
; CHECK-NEXT: }
190196
; CHECK-NEXT: {
191197
; CHECK-NEXT: r1 = mux(p1,#8,#0)
192198
; CHECK-NEXT: }
193199
; CHECK-NEXT: {
194-
; CHECK-NEXT: r3 = mux(p1,#2,#0)
200+
; CHECK-NEXT: r2 = mux(p1,#2,#0)
195201
; CHECK-NEXT: }
196202
; CHECK-NEXT: {
197-
; CHECK-NEXT: r5 = setbit(r1,#2)
203+
; CHECK-NEXT: if (!p0) r3 = #128
198204
; CHECK-NEXT: }
199205
; CHECK-NEXT: {
200-
; CHECK-NEXT: r6 = setbit(r3,#0)
206+
; CHECK-NEXT: r4 = mux(p0,#0,#32)
201207
; CHECK-NEXT: }
202208
; CHECK-NEXT: {
203-
; CHECK-NEXT: if (!p0) r2 = #128
209+
; CHECK-NEXT: r5 = setbit(r1,#2)
204210
; CHECK-NEXT: }
205211
; CHECK-NEXT: {
206-
; CHECK-NEXT: r4 = mux(p0,#0,#32)
212+
; CHECK-NEXT: r6 = setbit(r2,#0)
207213
; CHECK-NEXT: }
208214
; CHECK-NEXT: {
209215
; CHECK-NEXT: if (!p1) r5 = add(r1,#0)
210216
; CHECK-NEXT: }
211217
; CHECK-NEXT: {
212-
; CHECK-NEXT: if (!p1) r6 = add(r3,#0)
218+
; CHECK-NEXT: r1 = setbit(r3,#6)
213219
; CHECK-NEXT: }
214220
; CHECK-NEXT: {
215-
; CHECK-NEXT: r1 = setbit(r2,#6)
221+
; CHECK-NEXT: if (!p1) r6 = add(r2,#0)
216222
; CHECK-NEXT: }
217223
; CHECK-NEXT: {
218-
; CHECK-NEXT: r3 = setbit(r4,#4)
224+
; CHECK-NEXT: r2 = setbit(r4,#4)
219225
; CHECK-NEXT: }
220226
; CHECK-NEXT: {
221-
; CHECK-NEXT: r5 = or(r6,r5)
227+
; CHECK-NEXT: if (!p0) r4 = add(r2,#0)
222228
; CHECK-NEXT: }
223229
; CHECK-NEXT: {
224-
; CHECK-NEXT: if (!p0) r2 = add(r1,#0)
230+
; CHECK-NEXT: if (!p0) r3 = add(r1,#0)
225231
; CHECK-NEXT: }
226232
; CHECK-NEXT: {
227-
; CHECK-NEXT: if (!p0) r4 = add(r3,#0)
233+
; CHECK-NEXT: r2 = or(r6,r5)
228234
; CHECK-NEXT: }
229235
; CHECK-NEXT: {
230-
; CHECK-NEXT: r5 |= or(r4,r2)
236+
; CHECK-NEXT: r2 |= or(r4,r3)
231237
; CHECK-NEXT: }
232238
; CHECK-NEXT: {
233-
; CHECK-NEXT: memb(r0+#0) = r5
239+
; CHECK-NEXT: memb(r0+#0) = r2
234240
; CHECK-NEXT: }
235241
; CHECK-NEXT: {
236242
; CHECK-NEXT: jumpr r31

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