[RISCV] Return false for Zalasr load/store in isWorthFoldingAdd. (#136799)

The Zalasr load/store don't support reg-imm addressing modes so they
can't fold an ADDI.

Author: topperc

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -2599,6 +2599,8 @@ static bool isWorthFoldingAdd(SDValue Add) {
     if (User->getOpcode() == ISD::ATOMIC_STORE &&
         cast<AtomicSDNode>(User)->getVal() == Add)
       return false;
+    if (isStrongerThanMonotonic(cast<MemSDNode>(User)->getSuccessOrdering()))
+      return false;
   }
 
   return true;

llvm/test/CodeGen/RISCV/zalasr-offset-folding.ll

@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv32 -mattr=+a,+experimental-zalasr | FileCheck %s
+
+; Make sure we don't fold -1920 into the lw instruction because we still
+; need it for the sw.rl.
+
+define i32 @test(ptr %p) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui a1, 20
+; CHECK-NEXT:    addi a1, a1, -1920
+; CHECK-NEXT:    add a0, a0, a1
+; CHECK-NEXT:    li a1, 2
+; CHECK-NEXT:    sw.rl a1, (a0)
+; CHECK-NEXT:    lw a0, 0(a0)
+; CHECK-NEXT:    ret
+entry:
+  %gep0 = getelementptr [65536 x i32], ptr %p, i64 0, i32 20000
+  store atomic i32 2, ptr %gep0 seq_cst, align 4
+  %a = load i32, ptr %gep0
+  ret i32 %a
+}