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@jwnrt jwnrt commented Oct 24, 2025

When we expect ECC errors we have to ignore the fatal bus integrity alerts from Ibex otherwise the chip will repeatedly be interrupted.

This was missed by CI because the CW310 does not enable SecureIbex and the CW340 tests are not being run properly on this branch.

When we expect ECC errors we have to ignore the fatal bus integrity
alerts from Ibex otherwise the chip will repeatedly be interrupted.

Signed-off-by: James Wainwright <[email protected]>
@jwnrt jwnrt requested a review from a team as a code owner October 24, 2025 14:17
@jwnrt jwnrt requested review from a team, pamaury and rprakas-gsc and removed request for a team October 24, 2025 14:17
Comment on lines +286 to +289
// This is not done on CW305/CW310 FPGAs because interrupts for ECC errors are
// only triggered when the SecureIbex parameter is enabled. This parameter is
// disabled for these boards due to resource constraints. On CW340 and the
// other targets, this parameter is enabled.
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Put this comment on the expect_ecc_errors function?

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2 participants