ot_soc_dbg_ctrl: rewrite SoC debug controller implementation
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ot_soc_dbgctrl: rewrite SoC debug controller implementation
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ot_soc_dbgctrl: rewrite SoC debug controller implementationot_soc_dbg_ctrl: rewrite SoC debug controller implementation
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AlexJones0
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I'm completely unfamiliar with the SoC debug controller so I've generally reviewed the code for issues, and not any implementation specifics (outside of a couple of cases where the equivalent RTL was easy to cross-reference, or for common QEMU idioms). It generally LGTM outside of my comments though.
Aside: thanks for the very clear and isolated commits, it made this much easier to review!
Note: this signal is not available on EG 1.0.0 and should not be used with this Top. Also add missing ot_id in qemu_log messages. Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
…e code Signed-off-by: Emmanuel Blot <[email protected]>
Avoid using single var name and match other handlers. Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
also remove USB device clock from boot status to follow HW changes Signed-off-by: Emmanuel Blot <[email protected]>
…initions Signed-off-by: Emmanuel Blot <[email protected]>
from `ot_socdbg_ctrl` to match new HW Signed-off-by: Emmanuel Blot <[email protected]>
from `ot_socdbg_ctrl` to match new HW Signed-off-by: Emmanuel Blot <[email protected]>
A0 signals are no longer defined in new HW Signed-off-by: Emmanuel Blot <[email protected]>
…BLANK` to match new HW Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
this matches the HW definitions, although the actual bus is still DMI. Signed-off-by: Emmanuel Blot <[email protected]>
…u_boot` to match HW Signed-off-by: Emmanuel Blot <[email protected]>
there is no IRQ in new HW Signed-off-by: Emmanuel Blot <[email protected]>
to match new HW: there are two alert channels (fatal and recoverable) Signed-off-by: Emmanuel Blot <[email protected]>
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… management to match new HW Signed-off-by: Emmanuel Blot <[email protected]>
…ontroller Signed-off-by: Emmanuel Blot <[email protected]>
…tput signal for clients Signed-off-by: Emmanuel Blot <[email protected]>
- connect SoC debug controller to LC controller - define alert signals - tell the LC controller to decode signals for the SoC debug controller Signed-off-by: Emmanuel Blot <[email protected]>
to match new HW Signed-off-by: Emmanuel Blot <[email protected]>
to match HW naming Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
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AlexJones0
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Nov 12, 2025
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LGTM, though I haven't checked that the functionality matches the docs/RTL in most places.
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The SoC debug controller, which seems to be a Darjeeling-only device (although stored in
hw/ip/soc_dbg_ctrl) has been heavily modified since its original version.This PR rewrites the implementation based on current master implementation. There is unfortunately little to none way to test the implementation at the moment.