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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191126' into staging
target-arm queue: * handle FTYPE flag correctly in v7M exception return for v7M CPUs with an FPU (v8M CPUs were already correct) * versal: Add the CRP as unimplemented * Fix ISR_EL1 tracking when executing at EL2 * Honor HCR_EL2.TID3 trapping requirements # gpg: Signature made Tue 26 Nov 2019 14:11:50 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "[email protected]" # gpg: Good signature from "Peter Maydell <[email protected]>" [ultimate] # gpg: aka "Peter Maydell <[email protected]>" [ultimate] # gpg: aka "Peter Maydell <[email protected]>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20191126: target/arm: Honor HCR_EL2.TID3 trapping requirements target/arm: Fix ISR_EL1 tracking when executing at EL2 hw/arm: versal: Add the CRP as unimplemented target/arm: Fix handling of cortex-m FTYPE flag in EXCRET Signed-off-by: Peter Maydell <[email protected]>
2 parents 0d4f9d7 + 6a4ef4e commit 5f64adc

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4 files changed

+89
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lines changed

‎hw/arm/xlnx-versal.c

+2
Original file line numberDiff line numberDiff line change
@@ -257,6 +257,8 @@ static void versal_unimp(Versal *s)
257257
MM_CRL, MM_CRL_SIZE);
258258
versal_unimp_area(s, "crf", &s->mr_ps,
259259
MM_FPD_CRF, MM_FPD_CRF_SIZE);
260+
versal_unimp_area(s, "crp", &s->mr_ps,
261+
MM_PMC_CRP, MM_PMC_CRP_SIZE);
260262
versal_unimp_area(s, "iou-scntr", &s->mr_ps,
261263
MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
262264
versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,

‎include/hw/arm/xlnx-versal.h

+3
Original file line numberDiff line numberDiff line change
@@ -119,4 +119,7 @@ typedef struct Versal {
119119
#define MM_IOU_SCNTRS_SIZE 0x10000
120120
#define MM_FPD_CRF 0xfd1a0000U
121121
#define MM_FPD_CRF_SIZE 0x140000
122+
123+
#define MM_PMC_CRP 0xf1260000U
124+
#define MM_PMC_CRP_SIZE 0x10000
122125
#endif

‎target/arm/helper.c

+81-2
Original file line numberDiff line numberDiff line change
@@ -1934,8 +1934,11 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
19341934
CPUState *cs = env_cpu(env);
19351935
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
19361936
uint64_t ret = 0;
1937+
bool allow_virt = (arm_current_el(env) == 1 &&
1938+
(!arm_is_secure_below_el3(env) ||
1939+
(env->cp15.scr_el3 & SCR_EEL2)));
19371940

1938-
if (hcr_el2 & HCR_IMO) {
1941+
if (allow_virt && (hcr_el2 & HCR_IMO)) {
19391942
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
19401943
ret |= CPSR_I;
19411944
}
@@ -1945,7 +1948,7 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
19451948
}
19461949
}
19471950

1948-
if (hcr_el2 & HCR_FMO) {
1951+
if (allow_virt && (hcr_el2 & HCR_FMO)) {
19491952
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
19501953
ret |= CPSR_F;
19511954
}
@@ -5975,6 +5978,26 @@ static const ARMCPRegInfo predinv_reginfo[] = {
59755978
REGINFO_SENTINEL
59765979
};
59775980

5981+
static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
5982+
bool isread)
5983+
{
5984+
if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {
5985+
return CP_ACCESS_TRAP_EL2;
5986+
}
5987+
5988+
return CP_ACCESS_OK;
5989+
}
5990+
5991+
static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
5992+
bool isread)
5993+
{
5994+
if (arm_feature(env, ARM_FEATURE_V8)) {
5995+
return access_aa64_tid3(env, ri, isread);
5996+
}
5997+
5998+
return CP_ACCESS_OK;
5999+
}
6000+
59786001
void register_cp_regs_for_features(ARMCPU *cpu)
59796002
{
59806003
/* Register all the coprocessor registers based on feature bits */
@@ -5998,70 +6021,86 @@ void register_cp_regs_for_features(ARMCPU *cpu)
59986021
{ .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
59996022
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
60006023
.access = PL1_R, .type = ARM_CP_CONST,
6024+
.accessfn = access_aa32_tid3,
60016025
.resetvalue = cpu->id_pfr0 },
60026026
/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
60036027
* the value of the GIC field until after we define these regs.
60046028
*/
60056029
{ .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
60066030
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
60076031
.access = PL1_R, .type = ARM_CP_NO_RAW,
6032+
.accessfn = access_aa32_tid3,
60086033
.readfn = id_pfr1_read,
60096034
.writefn = arm_cp_write_ignore },
60106035
{ .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
60116036
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
60126037
.access = PL1_R, .type = ARM_CP_CONST,
6038+
.accessfn = access_aa32_tid3,
60136039
.resetvalue = cpu->id_dfr0 },
60146040
{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
60156041
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
60166042
.access = PL1_R, .type = ARM_CP_CONST,
6043+
.accessfn = access_aa32_tid3,
60176044
.resetvalue = cpu->id_afr0 },
60186045
{ .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
60196046
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
60206047
.access = PL1_R, .type = ARM_CP_CONST,
6048+
.accessfn = access_aa32_tid3,
60216049
.resetvalue = cpu->id_mmfr0 },
60226050
{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
60236051
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
60246052
.access = PL1_R, .type = ARM_CP_CONST,
6053+
.accessfn = access_aa32_tid3,
60256054
.resetvalue = cpu->id_mmfr1 },
60266055
{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
60276056
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
60286057
.access = PL1_R, .type = ARM_CP_CONST,
6058+
.accessfn = access_aa32_tid3,
60296059
.resetvalue = cpu->id_mmfr2 },
60306060
{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
60316061
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
60326062
.access = PL1_R, .type = ARM_CP_CONST,
6063+
.accessfn = access_aa32_tid3,
60336064
.resetvalue = cpu->id_mmfr3 },
60346065
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
60356066
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
60366067
.access = PL1_R, .type = ARM_CP_CONST,
6068+
.accessfn = access_aa32_tid3,
60376069
.resetvalue = cpu->isar.id_isar0 },
60386070
{ .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
60396071
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
60406072
.access = PL1_R, .type = ARM_CP_CONST,
6073+
.accessfn = access_aa32_tid3,
60416074
.resetvalue = cpu->isar.id_isar1 },
60426075
{ .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
60436076
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
60446077
.access = PL1_R, .type = ARM_CP_CONST,
6078+
.accessfn = access_aa32_tid3,
60456079
.resetvalue = cpu->isar.id_isar2 },
60466080
{ .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
60476081
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
60486082
.access = PL1_R, .type = ARM_CP_CONST,
6083+
.accessfn = access_aa32_tid3,
60496084
.resetvalue = cpu->isar.id_isar3 },
60506085
{ .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
60516086
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
60526087
.access = PL1_R, .type = ARM_CP_CONST,
6088+
.accessfn = access_aa32_tid3,
60536089
.resetvalue = cpu->isar.id_isar4 },
60546090
{ .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
60556091
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
60566092
.access = PL1_R, .type = ARM_CP_CONST,
6093+
.accessfn = access_aa32_tid3,
60576094
.resetvalue = cpu->isar.id_isar5 },
60586095
{ .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
60596096
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
60606097
.access = PL1_R, .type = ARM_CP_CONST,
6098+
.accessfn = access_aa32_tid3,
60616099
.resetvalue = cpu->id_mmfr4 },
60626100
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
60636101
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
60646102
.access = PL1_R, .type = ARM_CP_CONST,
6103+
.accessfn = access_aa32_tid3,
60656104
.resetvalue = cpu->isar.id_isar6 },
60666105
REGINFO_SENTINEL
60676106
};
@@ -6182,164 +6221,204 @@ void register_cp_regs_for_features(ARMCPU *cpu)
61826221
{ .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
61836222
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
61846223
.access = PL1_R, .type = ARM_CP_NO_RAW,
6224+
.accessfn = access_aa64_tid3,
61856225
.readfn = id_aa64pfr0_read,
61866226
.writefn = arm_cp_write_ignore },
61876227
{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
61886228
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
61896229
.access = PL1_R, .type = ARM_CP_CONST,
6230+
.accessfn = access_aa64_tid3,
61906231
.resetvalue = cpu->isar.id_aa64pfr1},
61916232
{ .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
61926233
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
61936234
.access = PL1_R, .type = ARM_CP_CONST,
6235+
.accessfn = access_aa64_tid3,
61946236
.resetvalue = 0 },
61956237
{ .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
61966238
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
61976239
.access = PL1_R, .type = ARM_CP_CONST,
6240+
.accessfn = access_aa64_tid3,
61986241
.resetvalue = 0 },
61996242
{ .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
62006243
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
62016244
.access = PL1_R, .type = ARM_CP_CONST,
6245+
.accessfn = access_aa64_tid3,
62026246
/* At present, only SVEver == 0 is defined anyway. */
62036247
.resetvalue = 0 },
62046248
{ .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62056249
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
62066250
.access = PL1_R, .type = ARM_CP_CONST,
6251+
.accessfn = access_aa64_tid3,
62076252
.resetvalue = 0 },
62086253
{ .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62096254
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
62106255
.access = PL1_R, .type = ARM_CP_CONST,
6256+
.accessfn = access_aa64_tid3,
62116257
.resetvalue = 0 },
62126258
{ .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62136259
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
62146260
.access = PL1_R, .type = ARM_CP_CONST,
6261+
.accessfn = access_aa64_tid3,
62156262
.resetvalue = 0 },
62166263
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
62176264
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
62186265
.access = PL1_R, .type = ARM_CP_CONST,
6266+
.accessfn = access_aa64_tid3,
62196267
.resetvalue = cpu->id_aa64dfr0 },
62206268
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
62216269
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
62226270
.access = PL1_R, .type = ARM_CP_CONST,
6271+
.accessfn = access_aa64_tid3,
62236272
.resetvalue = cpu->id_aa64dfr1 },
62246273
{ .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62256274
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
62266275
.access = PL1_R, .type = ARM_CP_CONST,
6276+
.accessfn = access_aa64_tid3,
62276277
.resetvalue = 0 },
62286278
{ .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62296279
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
62306280
.access = PL1_R, .type = ARM_CP_CONST,
6281+
.accessfn = access_aa64_tid3,
62316282
.resetvalue = 0 },
62326283
{ .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
62336284
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
62346285
.access = PL1_R, .type = ARM_CP_CONST,
6286+
.accessfn = access_aa64_tid3,
62356287
.resetvalue = cpu->id_aa64afr0 },
62366288
{ .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
62376289
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
62386290
.access = PL1_R, .type = ARM_CP_CONST,
6291+
.accessfn = access_aa64_tid3,
62396292
.resetvalue = cpu->id_aa64afr1 },
62406293
{ .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62416294
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
62426295
.access = PL1_R, .type = ARM_CP_CONST,
6296+
.accessfn = access_aa64_tid3,
62436297
.resetvalue = 0 },
62446298
{ .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62456299
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
62466300
.access = PL1_R, .type = ARM_CP_CONST,
6301+
.accessfn = access_aa64_tid3,
62476302
.resetvalue = 0 },
62486303
{ .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
62496304
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
62506305
.access = PL1_R, .type = ARM_CP_CONST,
6306+
.accessfn = access_aa64_tid3,
62516307
.resetvalue = cpu->isar.id_aa64isar0 },
62526308
{ .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
62536309
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
62546310
.access = PL1_R, .type = ARM_CP_CONST,
6311+
.accessfn = access_aa64_tid3,
62556312
.resetvalue = cpu->isar.id_aa64isar1 },
62566313
{ .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62576314
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
62586315
.access = PL1_R, .type = ARM_CP_CONST,
6316+
.accessfn = access_aa64_tid3,
62596317
.resetvalue = 0 },
62606318
{ .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62616319
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
62626320
.access = PL1_R, .type = ARM_CP_CONST,
6321+
.accessfn = access_aa64_tid3,
62636322
.resetvalue = 0 },
62646323
{ .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62656324
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
62666325
.access = PL1_R, .type = ARM_CP_CONST,
6326+
.accessfn = access_aa64_tid3,
62676327
.resetvalue = 0 },
62686328
{ .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62696329
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
62706330
.access = PL1_R, .type = ARM_CP_CONST,
6331+
.accessfn = access_aa64_tid3,
62716332
.resetvalue = 0 },
62726333
{ .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62736334
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
62746335
.access = PL1_R, .type = ARM_CP_CONST,
6336+
.accessfn = access_aa64_tid3,
62756337
.resetvalue = 0 },
62766338
{ .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62776339
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
62786340
.access = PL1_R, .type = ARM_CP_CONST,
6341+
.accessfn = access_aa64_tid3,
62796342
.resetvalue = 0 },
62806343
{ .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
62816344
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
62826345
.access = PL1_R, .type = ARM_CP_CONST,
6346+
.accessfn = access_aa64_tid3,
62836347
.resetvalue = cpu->isar.id_aa64mmfr0 },
62846348
{ .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
62856349
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
62866350
.access = PL1_R, .type = ARM_CP_CONST,
6351+
.accessfn = access_aa64_tid3,
62876352
.resetvalue = cpu->isar.id_aa64mmfr1 },
62886353
{ .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62896354
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
62906355
.access = PL1_R, .type = ARM_CP_CONST,
6356+
.accessfn = access_aa64_tid3,
62916357
.resetvalue = 0 },
62926358
{ .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62936359
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
62946360
.access = PL1_R, .type = ARM_CP_CONST,
6361+
.accessfn = access_aa64_tid3,
62956362
.resetvalue = 0 },
62966363
{ .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62976364
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
62986365
.access = PL1_R, .type = ARM_CP_CONST,
6366+
.accessfn = access_aa64_tid3,
62996367
.resetvalue = 0 },
63006368
{ .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63016369
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
63026370
.access = PL1_R, .type = ARM_CP_CONST,
6371+
.accessfn = access_aa64_tid3,
63036372
.resetvalue = 0 },
63046373
{ .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63056374
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
63066375
.access = PL1_R, .type = ARM_CP_CONST,
6376+
.accessfn = access_aa64_tid3,
63076377
.resetvalue = 0 },
63086378
{ .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63096379
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
63106380
.access = PL1_R, .type = ARM_CP_CONST,
6381+
.accessfn = access_aa64_tid3,
63116382
.resetvalue = 0 },
63126383
{ .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
63136384
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
63146385
.access = PL1_R, .type = ARM_CP_CONST,
6386+
.accessfn = access_aa64_tid3,
63156387
.resetvalue = cpu->isar.mvfr0 },
63166388
{ .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
63176389
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
63186390
.access = PL1_R, .type = ARM_CP_CONST,
6391+
.accessfn = access_aa64_tid3,
63196392
.resetvalue = cpu->isar.mvfr1 },
63206393
{ .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
63216394
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
63226395
.access = PL1_R, .type = ARM_CP_CONST,
6396+
.accessfn = access_aa64_tid3,
63236397
.resetvalue = cpu->isar.mvfr2 },
63246398
{ .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63256399
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
63266400
.access = PL1_R, .type = ARM_CP_CONST,
6401+
.accessfn = access_aa64_tid3,
63276402
.resetvalue = 0 },
63286403
{ .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63296404
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
63306405
.access = PL1_R, .type = ARM_CP_CONST,
6406+
.accessfn = access_aa64_tid3,
63316407
.resetvalue = 0 },
63326408
{ .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63336409
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
63346410
.access = PL1_R, .type = ARM_CP_CONST,
6411+
.accessfn = access_aa64_tid3,
63356412
.resetvalue = 0 },
63366413
{ .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63376414
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
63386415
.access = PL1_R, .type = ARM_CP_CONST,
6416+
.accessfn = access_aa64_tid3,
63396417
.resetvalue = 0 },
63406418
{ .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63416419
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
63426420
.access = PL1_R, .type = ARM_CP_CONST,
6421+
.accessfn = access_aa64_tid3,
63436422
.resetvalue = 0 },
63446423
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
63456424
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,

‎target/arm/m_helper.c

+3-4
Original file line numberDiff line numberDiff line change
@@ -2233,19 +2233,18 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
22332233
if (env->v7m.secure) {
22342234
lr |= R_V7M_EXCRET_S_MASK;
22352235
}
2236-
if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
2237-
lr |= R_V7M_EXCRET_FTYPE_MASK;
2238-
}
22392236
} else {
22402237
lr = R_V7M_EXCRET_RES1_MASK |
22412238
R_V7M_EXCRET_S_MASK |
22422239
R_V7M_EXCRET_DCRS_MASK |
2243-
R_V7M_EXCRET_FTYPE_MASK |
22442240
R_V7M_EXCRET_ES_MASK;
22452241
if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) {
22462242
lr |= R_V7M_EXCRET_SPSEL_MASK;
22472243
}
22482244
}
2245+
if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) {
2246+
lr |= R_V7M_EXCRET_FTYPE_MASK;
2247+
}
22492248
if (!arm_v7m_is_handler_mode(env)) {
22502249
lr |= R_V7M_EXCRET_MODE_MASK;
22512250
}

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