Fix CDC issue: Synchronize i_hsb_stat[0] in bootp module#109
Fix CDC issue: Synchronize i_hsb_stat[0] in bootp module#109umairsiddiqui-digitek wants to merge 1 commit into
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// i_hsb_stat[0] is generated in ptp_top.sv @ i_ptp_clk, // therefore, in bootp block it need to be sync on i_hif_clk Signed-off-by: umairsiddiqui-digitek <41374313+umairsiddiqui-digitek@users.noreply.github.com>
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WalkthroughThe BOOTP module in bootp.sv now synchronizes the i_hsb_stat input into the i_clk clock domain using a new data_sync instance, producing i_hsb_stat_sync. The bootp_vend_data field is updated to use this synchronized signal instead of the raw i_hsb_stat. ChangesBOOTP clock-domain sync
Estimated code review effort: 1 (Trivial) | ~5 minutes Related IssuesNone found. Related PRsNone found. Suggested labels: fpga, hardware Suggested reviewers: None identified. Poem: 🐰 A signal once raced through the clock's domain, / Now synced and steady, no more strain. / Through data_sync it hops in line, / bootp_vend_data reads it fine. / A tiny fix, a rabbit's cheer! 🎉 🚥 Pre-merge checks | ✅ 4✅ Passed checks (4 passed)
Comment |
Hi,
I noticed a Clock Domain Crossing (CDC) issue where the signal
i_hsb_statin thebootp.svmodule is being used without proper synchronization.Details:
Currently, only bit-0 (i_hsb_stat[0]) is connected in bootp.sv (Line 330).
holoscan-sensor-bridge/fpga/nv_hsb_ip/top/HOLOLINK_top.sv
Line 330 in fc2a6cf
This net is driven by the output signal o_ptp_en_sync_rx from the ptp_top block, as seen in ptp_top.sv (Line 58).
holoscan-sensor-bridge/fpga/nv_hsb_ip/ptp/ptp_top.sv
Line 58 in fc2a6cf
Problem:
The i_hsb_stat[0] signal is generated in the ptp_top domain clocked by i_ptp_clk. However, the bootp block operates on i_hif_clk. Using this signal directly without synchronization can lead to metastability.
Solution:
This PR adds the necessary synchronization logic to safely cross i_hsb_stat[0] over to the i_hif_clk domain before it is consumed by the bootp block.
Regards,
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