Specified clk input/outputs

source/Hardware Guide/Breakout Board/index.rst

@@ -14,7 +14,10 @@ data IO.
 
 :Design Repository: https://github.com/open-ephys/onix-breakout
 :Compatibility: :ref:`pcie_host`, :ref:`headstage_64`,
-                :ref:`headstage_neuropix1`, :ref:`miniscopes`
+                :ref:`headstage_neuropix1`, :ref:`miniscopes`,
+                :doc:`../Headstages/headstage-neuropix-1e`, 
+                :doc:`../Headstages/headstage-neuropix-2e`,
+                :doc:`../Headstages/headstage-rhs2116`
 
 
 .. _breakout_overview:
@@ -33,21 +36,21 @@ Features
 -------------------------
 The Breakout Board provides access to the following IO:
 
-- 2x headstage port feed-throughs, each with a power switch
-- 3x, passive, high-speed clock feed-throughs
+- 2x headstage port feed-throughs, each with a power switch.
+- 3x, passive, high-speed clock feed-throughs. These can be used to connect to the two clock inputs and one clock output on the PCIe controller.
 - 12x passive, ESD-protected, analog feed-throughs.
-- BNC, ribbon, or direct wire access to 12 analog inputs or outputs
+- BNC, ribbon, or direct wire access to 12 analog inputs or outputs. These have a ±10V range and are sampled at 100 kHz.
 - Ribbon cable or direct, wire-access to 8 digital outputs and 8 digital
-  inputs. These are 5V compliant.
-- `HARP bus <https://www.cf-hw.org/harp>`__ controller
+  inputs. These are 5V compliant and are sampled at 5 MHz.
+- `HARP <https://harp-tech.org/articles/about.html>`__ synchronization clock input bus
 
 Additionally, it has the following features:
 
-- Lots of indication LEDs
+- Lots of indication LEDs.
 - 6 buttons for marking experimental events for or triggering software actions.
 - Rugged M6 and 1/4-20 mounting holes for both metric and imperial optical
-  tables
-- 19" rack compatibility
+  tables.
+- 19" rack compatibility.
 - Fully open-source gateware and made using an open-source FPGA toolchain
   (`yosys <https://yosyshq.net/yosys/>`__ & `nextpnr
-  <https://github.com/YosysHQ/nextpnr>`__)
+  <https://github.com/YosysHQ/nextpnr>`__).

source/Hardware Guide/Breakout Board/setup.rst

@@ -15,9 +15,8 @@ PCIe host is connected to a breakout board using the following connections:
    power to the Breakout Board.
 #. Headstage links (Required for headstages): A single MMCX coaxial cable is
    used for each headstage port.
-#. High speed clocks (Optional): A single MMCX caoxial cable is used for each
+#. High speed clocks (Optional): A single MMCX coaxial cable is used for each
    clock signal
-#. HARP (Optional): A 3.5mm audio jack
 #. Configuration (Optional): Micro USB used to update the breakout gateware.
 
 .. image:: /_static/images/breakout/breakout_host_connections_callouts.png
@@ -33,7 +32,7 @@ each of these signal lines are acquired.
 
 .. note:: There may be more IO present on the breakout board than is available
     on a particular host board. For instance, :ref:`pcie_host` has two coaxial
-    links, but the breakout board provides four. This is is by design. The breakout
+    links, but the v1.5beta breakout board provides four. This is is by design. The breakout
     is designed to be compatible with future host hardware.
 
 Reset Button
@@ -79,11 +78,13 @@ Plug in MMCX coaxial connections for headstage ports and clock signals.
 - Use the MMCX to MMCX cable to connect a headstage port on the
   :ref:`pcie_host` to the breakout board. A single cable is required for
   each headstage port.
-- Make sure that port letter (A, B, C, D) on the breakout matches the port
+- Make sure that port letter (A, B) on the breakout matches the port
   letter on the PCIe host.
-- Additional MMCX cables can be used to connect the optional clock IO ports
-  on the PCIe host board to the clock ports on the breakout board.  These
-  are passive, 50-ohm transmission lines so the order does not matter.
+- If you are feeding the clock inputs/outputs from the controller through 
+  the breakout board, make sure that the port number (0, 1, 2) on the breakout
+  board matches the port number on the PCIe host (0 In, 1 In, 2 Out). Older 3D printed versions of 
+  the PCIe bracket label the clock ports as I\ :sub:`0`\, I\ :sub:`1`\, and O - 
+  these should connect to the breakout board ports 0, 1, 2, respectively.
 
 .. warning:: The MMCX connectors can be damaged if they are removed
   improperly. See :ref:`this link <mmcx_cable>` for information on how to

source/Hardware Guide/PCIe Host/index.rst

@@ -21,6 +21,9 @@ equipment.
 :Design Repository: https://github.com/open-ephys/onix-fmc-host
 :Compatibility: :ref:`headstage_64`,
                 :ref:`headstage_neuropix1`, :ref:`miniscopes`
-
+                :doc:`../Headstages/headstage-neuropix-1e`, 
+                :doc:`../Headstages/headstage-neuropix-2e`,
+                :doc:`../Headstages/headstage-rhs2116`
+
 .. figure:: /_static/images/pcie-host/pcie-host_nereid_fmc-host-1r4.jpg
     :align: center

source/Hardware Guide/PCIe Host/overview.rst

@@ -21,6 +21,7 @@ carrier board.
   - 8x digital inputs
   - 8x digital outputs
   - 12x analog outputs or inputs (±10V)
+  - 2x clock inputs, 1x clock output
 
 - Multi-board synchronization and triggering to increase number of headstages
   and IO