Replace teensy with RP235xB

[cjsha]

From this first commit, some parts might need to be rotated in the CPL file. JLCPCB was displaying many parts with incorrect orientation in their representation of parts populated on the PCB.

fix #2

[jonnew]

The power switch action is weak and probably it should be removed. The power switch is currently a cold switch that toggles the enable for generating VCC. However, isolated power is derived directly from VBUS:

Thus the power switch would do nothing in the case of e.g. some malfunction (remember that the user can actually program this thing themselves) and they would be forced to remove the USB cable anyway to turn the thing off. For this reason, the power switch actually adds confusion. IMO, the power switch should simply be removed as for fully USB power devices, its quite an uncommon motif. Try to think of a device that is powered by usb (no barrel or AC connection) and has a power switch.

[cjsha]

I took the switch circuit from the ephys test board without thinking enough about it, my bad

[cjsha]

From filcarv:

1. The panels still say v0.18. I believe they should say revB.
2. Put the Silkscreens on top of copper or no-copper. Sometimes the silk in the transitions between copper and no-copper looks very ugly and we need to discard some PCBs.
3. The panel is what users see first. The internal electronics may be outstanding, but the device’s look and feel is defined by the enclosure. Aligning labels with their corresponding holes/connectors may be a good practice for clarity and usability.
4. We've decoupled FED3.2's shield from ground. If you think this makes sense here as well, you can copy-paste the circuit from here (or, at least, use the same component cases because we already have them in stock). https://github.com/KravitzLabDevices/FED3/tree/main/Electronics/v7.6
5. In the previous version the external connector (J1) was connected to pins that allow PWM, SPI, ADC, DAC, and I2C. It seems that it was intended to allow a further expansion to be very versatile. Does the current revB also allow for these?
6. When "updating PCB from Schematic" I saw a list of "Changes to Be Applied". This means the schematic and layout are not synchronized? I'm not a KiCAD pro, maybe this observation doesn't make any sense.
7. What's the function of the !BOOT_SEL switch (SW3)?
8. I don't think this comment is correct. I believe this should be for pins 66 and 67.
9. The USB lines are going down (top-to-bottom) and up (bottom-to-top) during is way from the connector to the uP.
   I'm not sure if it's not a better idea to keep them in the same top layer. Maybe moving some QSPI line to bottom will make room to keep the USB lines in the top.
10. Please keep the SN label at the top. I'm sending two suggestions of placement.

[cjsha]

7. What's the function of the !BOOT_SEL switch (SW3)?

This button can be held while power cycling the rp mcu in order to enter the bootloader

[cjsha]

I addressed filcarv's feedback. Below are some notes on that feedback.

---

4. We've decoupled FED3.2's shield from ground.

We've decided not to do this on stimjim revB.

5. In the previous version the external connector (J1) was connected to pins that allow PWM, SPI, ADC, DAC, and I2C. It seems that it was intended to allow a further expansion to be very versatile. Does the current revB also allow for these?

• PWM: ✅
• I2C: ✅
• DAC: ❌ not possible, no DAC on any RP MCU
• ADC: ❌, though I can pin one out if necessary @jonnew @filcarv
• SPI: we're using both dedicated SPI blocks in the RP2040, but they can probably find an SPI implementation using the PIO

6. When "updating PCB from Schematic" I saw a list of "Changes to Be Applied". This means the schematic and layout are not synchronized? I'm not a KiCAD pro, maybe this observation doesn't make any sense.

I updated PCB from schematic. Even immediately after doing so, you'll probably get a bunch of lines with the designators of the parts that KiCAD is going to attempt to update. You can try again and see if the same thing occurs.

Everything else in the ten points provided were changed.

---

Here are the new panels btw:

Btw, the BNC PN is different but the old ones should still fit in the panel cutout.

[jonnew]

@filcarv With respect to point 4, the decoupling serves no purpose. This is because the Shield and ground or shorted inside the cable itself. So, if anything, the FED3's connection should be updated.

[cjsha]

jon said remove "rev. B" from the PCB panels. Those aren't rev. B, the inner PCB is.

[jonnew]

1. Should the wire push terminals be removed? Its generally not a good idea to to parallel the outputs from an instrument, especially one that generally produces a current since the user might be tempted to plug two things in simultaneously. Instead of these two things, we could just provide the following:

https://www.walmart.com/ip/BNC-Video-Baluns-Adapter-BNC-Male-Connector-BNC-Male-Plug-to-2-Pin-Screw-Terminal-No-Solder-Wire-Clamp-BNC-Adapter/17669874377

I think to make changes minimal, I suggest simply marking the terminal block as DNP, removing it from the panel, and providing the above adapter with the device instead.

2. The "Input X" BNC connectors should be called "Trigger X". This is because they can either serve as trigger inputs to start stimuli or outputs to mark when they occur depending on a selectable mode in the device.

3. The "Program" Button should be labelled "Reset"

4. Add one of these, or maybe some clip thing, near the USB entry to connect PCB to the panel.

https://www.mouser.com/ProductDetail/PEM/SMTRAM3-7-5ET?qs=l4Gc20tDgJIyk%252Bzis07rYw%3D%3D

[cjsha]

The only change I made is fixing the curve on the upper right corner of the Ch.0/Ch.1 boxes. This is what the curve looked like before my commit:

I also moved one of the trigger labels like 0.15mm so they're fully aligned. It wouldn't have been noticeable in any case, but I figured I might as well make them line up.

---

I decided to put the 3D assembly together just to confirm. I figure it's better to safer than sorry as OEPS is on their last stimjim already, don't wanna make a mistake here. The GND thread step file is not there, but it seems like it will align from taking measurements on the PCB and looking at the part's datasheet.

accidentally deleted some silkscreen on the bottom screenshot, but it looks good.

[jonnew]

This is now in production. Since this device is already distributed, I would suggest we don't merge this PR until the hardware has been verified and firmware has to be created to support it. I did create a release targeting f08c5cb since this version of the hardware will exist internally

https://github.com/open-ephys/stimjim/releases/tag/rev-b

[cjsha]

• sw3 footprint doesn't fit perfectly
  
• R26 doesn't appear in iBOM
• Fix LED courtyard and move LED resistors. Move serial number sticker as well? so that it's not under the black LED plastic

Order (or change values/footprints in the schematic):

• Resistors:
  • 1k 0603
  • 5k 0603 (rev B assembled at OE populated with 4.99k 0402 instead)
  • 270 0805 (rev B assembled at OE populated with 330 0805 instead)
  • 2.2M 1210 (rev B assembled at OR populated with 2.2M axial instead)
• Capacitors:
  • 0.1u 0603
  • 2.2n 1210 (it's DNP, I guess it might not be necessary to order this, but we should remove it from the iBOM if not)
• smtra_m3-7-5et

[cjsha]

The screw holes in the new panel are a tad too small.

this is the major diameter of the screw provided by the company that made the enclosure:

[cjsha]

LEDS stick out too much.

[cjsha]

Use black enclosure instead of silver

[cjsha]

In the next revision, put all parts on top. not worth the effort.

And look at #7.

[cjsha]

Panels:

• Use buttonhead screw for grounding case.
• Provide access to side-mounting rails
• Print stimjim on front
• Make enclosure panels 2mm thick

[cjsha]

This is my attempt to fix most the problems with rev B (with verbal feedback from @jonnew as well as my own comments), but the following items remain:

• best way to add stimjim logo to front panel?
• should we put open ephys logo (probably on the back panel) as well?
• I have a question about the way AD7321's REFIN pin is decoupled. A 1uF decoupling cap connects REFIN to DGND and AGND's only connection to GND is directly through the DGND pad where as the datasheet says "the 2.5 V internal reference is available at the REFIN/OUT pin, which should be decoupled to AGND using a 680 nF capacitor". It's easy to change the capacitor value to match the datasheet, but I wasn't sure about the routing around the decoupling cap.
  
  

[cjsha]

The firmware contained in #6 provides enough proof-of-concept to help verify stimjim rev c before ordering it. I think there are basically three things that need to be true: the rp-stimijim must send accurate pulse trains (i.e. meeting pulse timing constraints and amplitude accuracy), and remove the ADC ripple.

stimjim paper for reference.

Accuracy of pulse timings

The stimjim paper specifies 20us stage duration. Also:

While worst case errors of 2 µs (IPI) and 10 µs (PW) were detected, typical performance exceeded the temporal resolution of our test equipment. For example, IPI and PW standard deviations were typically less than 0.5 µs, which was the temporal resolution of our test equipment.

The 20us pulse timing constraint and the IPI/PW standard deviations specification are both met in the screenshot below and can be further improved with changes to the firmware:

Accuracy of voltage/current output and measurement

From −10V to +10V (the range of our test equipment), Stimjim produced accurate voltage and current amplitudes, with maximal errors of less than 40 mV and 2.5 µA

In the far extremes of +/-10V range, the error that I measured exceed the error specified in the paper. The following screenshots show data and a plot of the error across the entire range of the stimjim. Each screenshot contains two error measurements:

• the error between the amplitude set by the user using the "V" command and the amplitude measured by the oscope
• the error between amplitude measured by the oscope and the amplitude measured by the stimjim ADC

These measurements were taken by connecting the BNC output of channel 0 to an oscope input. The measurements for the second and third screenshots also include a 3k Ohm resistor between ch0's positive and negative terminals. Channel 0 has a bodged op-amp which serves as a unity voltage follower to reduce the ADC ripple (as discussed in the next section). For each row of the table, I used the "V" command followed by an "E" command to set the output of the channel and to measure the output of the channel respectively. I also recorded an averaged value from oscope.

Voltage measurements, no load besides the 1MOhm oscope input impedance.

Voltage measurements, 3k Ohm load

Current measurements, 3k Ohm load

here's a link to the data that produced the above screenshots.

ADC Ripple

There is already a report for this in #7. d1b0eda implements the op-amp unity buffer mentioned as described in that issue.