TCDM and uDMA I2C spec updates #350
Conversation
| uDMA I2C uses the Tx channel interface to read the data from the interleaved (L2) memory via the uDMA Core. It transmits the read data to the external device. uDMA I2C uses the Rx channel interface to store the data received from the external device in interleaved (L2) memory. | ||
| Refer to `uDMA subsystem <https://github.com/openhwgroup/core-v-mcu/blob/master/docs/doc-src/udma_subsystem.rst>`_ for more information about the Tx and Rx channel functionality of uDMA Core. | ||
|
|
||
| Dual clock FIFO |
There was a problem hiding this comment.
I think (please confirm) that this section and all sections to I2C Controller are common with all the other uDMA peripherals. If that is the case, it would be better two document it once and simply refer to it here.
|
|
||
| RX_SIZE offset = 0x04 | ||
| ~~~~~~~~~~~~~~~~~~~~~ | ||
| **NOTE:** No functionality is implemented in RTL and always returns 0x0. |
There was a problem hiding this comment.
Is this accurate? The STATUS CSR always returns 0x0?
There was a problem hiding this comment.
Yes, its hardcoded to return 0x0 in RTL
| +------------+-------+------+------------+-------------------------------------------------------------+ | ||
| Clock Enable, Rest uDMA I2C | ||
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
| - Configure the uDMA Core's PERIPH_CLK_ENABLE CSR to enable uDMA I2C's peripheral clock. |
There was a problem hiding this comment.
Can you provide more details about how the `PERIPH_CLK_ENABLE CSR is used to set the data rate of the I2C?
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
| - err_o | ||
|
|
||
| ``**Note**:: Currently, no details are provided for this pin.`` |
There was a problem hiding this comment.
This statement is a little confusing. Do you mean that the operation of the err_o is undefined?
There was a problem hiding this comment.
the err_o signal is left unconnected internally, so its behavior is undefined.
| - 4 TCDM interfaces for eFPGA provide high speed access to the CORE-V-MCU memory. | ||
| - Provides a JTAG debug interface. | ||
| - Supports a 32-bit address width, 32-bit data width, and 32-bit byte enable (BE) width. | ||
| - Support below network topologies |
There was a problem hiding this comment.
Which of these does it support, or is the network topology configurable?
There was a problem hiding this comment.
The network topology is not configurable
There was a problem hiding this comment.
Hi @cst-pooja, this is a very comprehensive contribution! The diagrams related to the TCDM are particularly impressive. Of course, I do have a few comments/questions and these should be resolved before we merge in this PR.
Lastly, I see that you are not covered by the Eclipse Contributor Agreement. This must be done before we can accept this PR. Please speak with one of your colleagues about that.
2 participants
No description provided.