uDMA SDIO doc updates #353
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| Refer to `uDMA subsystem <https://github.com/openhwgroup/core-v-mcu/blob/master/docs/doc-src/udma_subsystem.rst>`_ for more information about the Tx and Rx channel functionality of uDMA Core. | ||
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| - If the response is enabled, set the state to ST_RX_START. | ||
| Dual clock FIFO |
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I think this is a repeat of similar sub-sections of the uDM QSPI chapter. If it truly is a repeat, please remove this and replace it with a reference to the relevant section in the QSPI chapter.
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There are very subtle differences in terms of buffer depth; hence, a separate section was created. Let me know if you still need the update.
docs/doc-src/ip-blocks/udma_sdio.rst
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| `Start bit -> Data -> CRC - > End` | ||
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| input logic clock_enable_i, | ||
| To receive response, uMDA QSPI expects `sddata_i` pin to have value 0(indicating start bit) within BLOCK_NUM clock cycles. If uDMA SDIO does not receive response from the external device within BLOCK_NUM `sdclk_o` clock cycle, it updates the Rx STATUS to STATUS_RSP_TIMEOUT and does not wait for the response. |
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Typo: uMDA should be uDMA.
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Fixed in the latest version.
docs/doc-src/ip-blocks/udma_sdio.rst
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| receive the data and enter the data into FIFO and another module | ||
| connected to the destination and works on sending the FIFO data to | ||
| destination. | ||
| - Configure uDMA Core's PERIPH_CLK_ENABLE to enable uDMA SDIO's peripheral clock. A peripheral clock is used to calculate the baud rate in uDMA SDIO. |
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I believe that the baud rate depends on the frequency of the system clock and a value of a specific CSR. It would be good to document that relationship here as a simple formula.
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Fixed in the latest version.
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Hi @cst-aditya. I this almost ready to merge in. I have left a couple of (minor) comments.
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