feat: Add support for SVNAPOT extension #3094
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@JeanRochCoulon got some issues while rebasing the branch. So, created this new Pull Request and closed the previous one. Please look into it. |
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@jayishnu637
I have added some comments. Which I think needs to be resolved first, then move forward.
I have some concerns on your svnapot extension micro-architecture.
I'm reviewing your previous PR on Saturday. But you closed that one to rebase with main. Therefore, I’ve shifted my comments to this PR
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@YazanHussnain-10x I've pushed a new commit addressing all the points you raised. Thanks for pointing those issues out. |
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Hi team, I've pushed fixes for the previous compilation errors in this PR. However, the only test failing is "Environment check" with a generic Environment failure detected error (Job ID: 273740): Environment failure detected. Some reports might be missing. Any guidance on how to resolve this environment issue would be greatly appreciated. |
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Hello @jayishnu637 I relaunched the CI. It passes right now. |
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Hi @jayishnu637 ,
I have left some more comments.
I looked at the cva6_mmu and cva6_ptw files so far. I'll read through the rest later.
Sorry to review so little each day, but I am working on it...
Not yet. I’ve added some additional comments and will be completing the rest of my review shortly. |
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Hi @YazanHussnain-10x, Thanks |
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Description
The CVA6 processor core lacked support for the RISC-V Svnapot (Naturally Aligned Power-of-Two) extension. The primary motivation for this feature is to improve MMU performance by allowing a single TLB entry to map a large, contiguous 64KiB memory region, thereby reducing TLB misses for memory-intensive applications. With this implementation Svnapot will be supported in CVA6 core.
Changes
1. Page Table Walker (cva6_ptw.sv):
The PTW now correctly detects a 64KiB NAPOT PTE (N=1, PPN[3:0] = 4'b1000).
Upon detection, it forwards the unmodified PTE to the TLB update interface.
A new signal, napot_bits, is propagated alongside the PTE to flag it as a NAPOT entry for the TLB.
2. TLBs (cva6_tlb.sv and cva6_shared_tlb.sv):
The TLB storage (tags_q, content_q) has been extended to include the napot_bits field, allowing each entry to be identified as a standard or NAPOT page.
Tag Comparison Logic: The lookup logic has been significantly updated. When comparing tags for an entry where napot_bits is set, the lower 4 bits of the Virtual Page Number (VPN) are masked (ignored). This ensures that any virtual address within the 64KiB range correctly matches the single NAPOT TLB entry.
On-Hit PPN Patching: This is the core of the fix. Upon a successful tag match with a NAPOT entry, the final PPN is constructed by taking the stored PPN template and overwriting its lower 4 bits (PPN[3:0]) with the corresponding bits from the incoming virtual address (vaddr[15:12]).
3. Memory Management Unit (cva6_mmu.sv):
How to Test
Compile the CVA6 core with the changes from this pull request.
You may use the napot.S test from the official RISCV repository https://github.com/riscv-software-src/riscv-tests/tree/master/isa/rv64ssvnapot or the napot_dual.S test can be used
Run the napot directed tests.
The napot.S test should PASS without any timeout or failure.
CC @Jbalkind, @niwis