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Bump verif/core-v-verif from 60e5724 to d4b94d4 #3103

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Bump verif/core-v-verif from 60e5724 to d4b94d4 #3103

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2 changes: 1 addition & 1 deletion verif/core-v-verif
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Submodule core-v-verif updated 80 files
+8 −0 bin/README.md
+2 −2 bin/requirements.txt
+1 −1 cv32e40p/sim/core/Makefile
+32 −0 lib/cv_dv_utils/python/sim_cmd/README.md
+46 −0 lib/cv_dv_utils/python/sim_cmd/compile.py
+208 −0 lib/cv_dv_utils/python/sim_cmd/get_cmd.py
+26 −0 lib/cv_dv_utils/python/sim_cmd/module1_template.yaml
+24 −0 lib/cv_dv_utils/python/sim_cmd/module2_template.yaml
+107 −0 lib/cv_dv_utils/python/sim_cmd/run_reg.py
+52 −0 lib/cv_dv_utils/python/sim_cmd/run_test.py
+30 −0 lib/cv_dv_utils/python/sim_cmd/top_questa_template.yaml
+26 −0 lib/cv_dv_utils/python/sim_cmd/top_vcs_template.yaml
+17 −0 lib/cv_dv_utils/uvm/generic_agent/README.md
+6 −4 lib/cv_dv_utils/uvm/generic_agent/generic_agent.svh
+4 −19 lib/cv_dv_utils/uvm/generic_agent/generic_driver.svh
+1 −1 lib/cv_dv_utils/uvm/generic_agent/generic_monitor.svh
+10 −2 lib/cv_dv_utils/uvm/generic_agent/generic_sequencer.svh
+8 −3 lib/cv_dv_utils/uvm/generic_agent/generic_sequences.svh
+22 −1 lib/cv_dv_utils/uvm/memory_partition/memory_partitions_cfg.svh
+18 −0 lib/uvm_agents/uvma_axi5/example/README.md
+26 −0 lib/uvm_agents/uvma_axi5/example/simu/cv_dv_utils.yaml
+2 −0 lib/uvm_agents/uvma_axi5/example/simu/run.do
+2 −0 lib/uvm_agents/uvma_axi5/example/simu/run_test.do
+32 −0 lib/uvm_agents/uvma_axi5/example/simu/simulator_questa.yaml
+31 −0 lib/uvm_agents/uvma_axi5/example/simu/simulator_vcs.yaml
+31 −0 lib/uvm_agents/uvma_axi5/example/simu/uvma_axi5.yaml
+29 −0 lib/uvm_agents/uvma_axi5/example/simu/wave.do
+70 −0 lib/uvm_agents/uvma_axi5/example/sv/bp_virtual_sequence.svh
+55 −0 lib/uvm_agents/uvma_axi5/example/sv/dut_cfg_c.svh
+146 −0 lib/uvm_agents/uvma_axi5/example/sv/dut_env.sv
+151 −0 lib/uvm_agents/uvma_axi5/example/sv/dut_env_axi_ohg.sv
+36 −0 lib/uvm_agents/uvma_axi5/example/sv/dut_env_pkg.sv
+482 −0 lib/uvm_agents/uvma_axi5/example/sv/mem_protocol_checker.sv
+67 −0 lib/uvm_agents/uvma_axi5/example/test/base_test_c.svh
+111 −0 lib/uvm_agents/uvma_axi5/example/test/bursty_test_c.svh
+35 −0 lib/uvm_agents/uvma_axi5/example/test/test_pkg.sv
+1 −0 lib/uvm_agents/uvma_axi5/example/top/run.do
+2 −0 lib/uvm_agents/uvma_axi5/example/top/run_test.do
+165 −0 lib/uvm_agents/uvma_axi5/example/top/top.sv
+4 −0 lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_cfg.sv
+1 −0 lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_tdefs.sv
+3 −2 lib/uvm_agents/uvma_core_cntrl/uvma_core_cntrl_utils.sv
+44 −5 lib/uvm_agents/uvma_cvxif/src/comps/uvma_cvxif_drv.sv
+5 −5 lib/uvm_agents/uvma_cvxif/src/obj/uvma_cvxif_cfg.sv
+15 −19 lib/uvm_agents/uvma_cvxif/src/uvma_cvxif_assert.sv
+253 −49 lib/uvm_agents/uvma_isacov/cov/uvma_isacov_cov_model.sv
+84 −1 lib/uvm_agents/uvma_isacov/uvma_isacov_macros.sv
+3 −3 lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_slv_seq.sv
+2 −2 lib/uvm_agents/uvma_obi_memory/src/seq/uvma_obi_memory_vp_sig_writer_seq.sv
+18 −0 lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_1p2_assert.sv
+61 −31 lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_assert.sv
+1 −1 lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_macros.sv
+1 −1 mk/TOOLCHAIN.md
+1 −7 tools/vptool/vptool/vptool.yml
+33 −0 vendor/patches/riscv/riscv-isa-sim/0037-make-zifencei-optional.patch
+12 −0 vendor/patches/riscv/riscv-isa-sim/0042-fix-extension-reset.patch
+136 −0 vendor/patches/riscv/riscv-isa-sim/0043-allow-unmapped-mem-access.patch
+80 −0 vendor/patches/riscv/riscv-isa-sim/0044-cvxif-no-more-implicit-x10-dest-reg.patch
+112 −0 vendor/patches/riscv/riscv-isa-sim/0044-don-t-optimize-decode-for-addi.patch
+72 −0 vendor/patches/riscv/riscv-isa-sim/0045-spike-disasm-don-t-optimaze-jump-instructions.patch
+24 −0 vendor/patches/riscv/riscv-isa-sim/0046-no-pmp-config-via-device-trees.patch
+309 −50 vendor/riscv/riscv-isa-sim/customext/cvxif.cc
+10 −7 vendor/riscv/riscv-isa-sim/disasm/disasm.cc
+12 −3 vendor/riscv/riscv-isa-sim/disasm/isa_parser.cc
+1 −1 vendor/riscv/riscv-isa-sim/fesvr/SimDTM.cc
+2 −2 vendor/riscv/riscv-isa-sim/fesvr/fesvr_dpi.cc
+22 −3 vendor/riscv/riscv-isa-sim/riscv/Proc.cc
+6 −0 vendor/riscv/riscv-isa-sim/riscv/Proc.h
+34 −7 vendor/riscv/riscv-isa-sim/riscv/cvxif.h
+4 −6 vendor/riscv/riscv-isa-sim/riscv/cvxif_base.cc
+26 −0 vendor/riscv/riscv-isa-sim/riscv/encoding.h
+3 −0 vendor/riscv/riscv-isa-sim/riscv/extension.h
+1 −0 vendor/riscv/riscv-isa-sim/riscv/insns/fence_i.h
+2 −0 vendor/riscv/riscv-isa-sim/riscv/isa_parser.h
+16 −6 vendor/riscv/riscv-isa-sim/riscv/mmu.cc
+4 −1 vendor/riscv/riscv-isa-sim/riscv/mmu.h
+7 −0 vendor/riscv/riscv-isa-sim/riscv/overlap_list.h
+7 −3 vendor/riscv/riscv-isa-sim/riscv/processor.cc
+4 −1 vendor/riscv/riscv-isa-sim/riscv/sim.cc
+5 −0 vendor/riscv/riscv-isa-sim/spike_main/spike.cc
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