Skip to content

[rtl] CSR cleanup #167

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 5 commits into
base: main
Choose a base branch
from
Open

[rtl] CSR cleanup #167

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
ef5ac87
cycle and instret CSR registers added
szbieg Oct 18, 2023
79bf078
Merge branch 'openhwgroup:main' into feature/csrcleanup
szbieg Oct 25, 2023
07391f7
[rtl] mcountinhibit reset value set to disable cycle, instret and hpm…
szbieg Nov 2, 2023
640bb9f
Merge branch 'feature/csrcleanup' of github.com:NXP/openhwgroup-cve2 …
szbieg Nov 2, 2023
1c6f55d
corrected mcountinhibit_rst width
szbieg Nov 3, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
68 changes: 42 additions & 26 deletions rtl/cve2_cs_registers.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -156,6 +156,22 @@ module cve2_cs_registers #(
priv_lvl_e prv;
} dcsr_t;

typedef struct packed {
logic hpm12;
logic hpm11;
logic hpm10;
logic hpm9;
logic hpm8;
logic hpm7;
logic hpm6;
logic hpm5;
logic hpm4;
logic hpm3;
logic ir;
logic zero0;
logic cy;
} mcountinhibit_t;

// Interrupt and exception control signals
logic [31:0] exception_pc;

Expand Down Expand Up @@ -399,37 +415,29 @@ module cve2_cs_registers #(
CSR_MHPMEVENT3,
CSR_MHPMEVENT4, CSR_MHPMEVENT5, CSR_MHPMEVENT6, CSR_MHPMEVENT7,
CSR_MHPMEVENT8, CSR_MHPMEVENT9, CSR_MHPMEVENT10, CSR_MHPMEVENT11,
CSR_MHPMEVENT12, CSR_MHPMEVENT13, CSR_MHPMEVENT14, CSR_MHPMEVENT15,
CSR_MHPMEVENT16, CSR_MHPMEVENT17, CSR_MHPMEVENT18, CSR_MHPMEVENT19,
CSR_MHPMEVENT20, CSR_MHPMEVENT21, CSR_MHPMEVENT22, CSR_MHPMEVENT23,
CSR_MHPMEVENT24, CSR_MHPMEVENT25, CSR_MHPMEVENT26, CSR_MHPMEVENT27,
CSR_MHPMEVENT28, CSR_MHPMEVENT29, CSR_MHPMEVENT30, CSR_MHPMEVENT31: begin
CSR_MHPMEVENT12: begin
csr_rdata_int = mhpmevent[mhpmcounter_idx];
end

CSR_CYCLE,
CSR_MCYCLE,
CSR_INSTRET,
CSR_MINSTRET,
CSR_MHPMCOUNTER3,
CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER7,
CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER9, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11,
CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15,
CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19,
CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23,
CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27,
CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31: begin
CSR_MHPMCOUNTER12: begin
csr_rdata_int = mhpmcounter[mhpmcounter_idx][31:0];
end

CSR_CYCLEH,
CSR_MCYCLEH,
CSR_INSTRETH,
CSR_MINSTRETH,
CSR_MHPMCOUNTER3H,
CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H,
CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H,
CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H,
CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H,
CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H,
CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H,
CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H: begin
CSR_MHPMCOUNTER12H: begin
csr_rdata_int = mhpmcounter[mhpmcounter_idx][63:32];
end

Expand Down Expand Up @@ -593,11 +601,7 @@ module cve2_cs_registers #(
CSR_MHPMCOUNTER3,
CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER7,
CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER9, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11,
CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15,
CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19,
CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23,
CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27,
CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31: begin
CSR_MHPMCOUNTER12: begin
mhpmcounter_we[mhpmcounter_idx] = 1'b1;
end

Expand All @@ -606,11 +610,7 @@ module cve2_cs_registers #(
CSR_MHPMCOUNTER3H,
CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H,
CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H,
CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H,
CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H,
CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H,
CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H,
CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H: begin
CSR_MHPMCOUNTER12H: begin
mhpmcounterh_we[mhpmcounter_idx] = 1'b1;
end

Expand Down Expand Up @@ -1299,9 +1299,25 @@ module cve2_cs_registers #(
assign mcountinhibit = mcountinhibit_q;
end

// MCOUNTINHIBIT
localparam mcountinhibit_t MCOUNTINHIBIT_RST_VAL = '{cy: 1'b1,
zero0: 1'b0,
ir: 1'b1,
hpm3: 1'b1,
hpm4: 1'b0,
hpm5: 1'b0,
hpm6: 1'b0,
hpm7: 1'b0,
hpm8: 1'b0,
hpm9: 1'b0,
hpm10: 1'b0,
hpm11: 1'b0,
hpm12: 1'b0};


always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
mcountinhibit_q <= '0;
mcountinhibit_q <= 13'(MCOUNTINHIBIT_RST_VAL);
end else begin
mcountinhibit_q <= mcountinhibit_d;
end
Expand Down
61 changes: 4 additions & 57 deletions rtl/cve2_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -441,26 +441,9 @@ package cve2_pkg;
CSR_MHPMEVENT10 = 12'h32A,
CSR_MHPMEVENT11 = 12'h32B,
CSR_MHPMEVENT12 = 12'h32C,
CSR_MHPMEVENT13 = 12'h32D,
CSR_MHPMEVENT14 = 12'h32E,
CSR_MHPMEVENT15 = 12'h32F,
CSR_MHPMEVENT16 = 12'h330,
CSR_MHPMEVENT17 = 12'h331,
CSR_MHPMEVENT18 = 12'h332,
CSR_MHPMEVENT19 = 12'h333,
CSR_MHPMEVENT20 = 12'h334,
CSR_MHPMEVENT21 = 12'h335,
CSR_MHPMEVENT22 = 12'h336,
CSR_MHPMEVENT23 = 12'h337,
CSR_MHPMEVENT24 = 12'h338,
CSR_MHPMEVENT25 = 12'h339,
CSR_MHPMEVENT26 = 12'h33A,
CSR_MHPMEVENT27 = 12'h33B,
CSR_MHPMEVENT28 = 12'h33C,
CSR_MHPMEVENT29 = 12'h33D,
CSR_MHPMEVENT30 = 12'h33E,
CSR_MHPMEVENT31 = 12'h33F,
CSR_CYCLE = 12'hC00,
CSR_MCYCLE = 12'hB00,
CSR_INSTRET = 12'hC02,
CSR_MINSTRET = 12'hB02,
CSR_MHPMCOUNTER3 = 12'hB03,
CSR_MHPMCOUNTER4 = 12'hB04,
Expand All @@ -472,26 +455,9 @@ package cve2_pkg;
CSR_MHPMCOUNTER10 = 12'hB0A,
CSR_MHPMCOUNTER11 = 12'hB0B,
CSR_MHPMCOUNTER12 = 12'hB0C,
CSR_MHPMCOUNTER13 = 12'hB0D,
CSR_MHPMCOUNTER14 = 12'hB0E,
CSR_MHPMCOUNTER15 = 12'hB0F,
CSR_MHPMCOUNTER16 = 12'hB10,
CSR_MHPMCOUNTER17 = 12'hB11,
CSR_MHPMCOUNTER18 = 12'hB12,
CSR_MHPMCOUNTER19 = 12'hB13,
CSR_MHPMCOUNTER20 = 12'hB14,
CSR_MHPMCOUNTER21 = 12'hB15,
CSR_MHPMCOUNTER22 = 12'hB16,
CSR_MHPMCOUNTER23 = 12'hB17,
CSR_MHPMCOUNTER24 = 12'hB18,
CSR_MHPMCOUNTER25 = 12'hB19,
CSR_MHPMCOUNTER26 = 12'hB1A,
CSR_MHPMCOUNTER27 = 12'hB1B,
CSR_MHPMCOUNTER28 = 12'hB1C,
CSR_MHPMCOUNTER29 = 12'hB1D,
CSR_MHPMCOUNTER30 = 12'hB1E,
CSR_MHPMCOUNTER31 = 12'hB1F,
CSR_CYCLEH = 12'hC80,
CSR_MCYCLEH = 12'hB80,
CSR_INSTRETH = 12'hC82,
CSR_MINSTRETH = 12'hB82,
CSR_MHPMCOUNTER3H = 12'hB83,
CSR_MHPMCOUNTER4H = 12'hB84,
Expand All @@ -503,25 +469,6 @@ package cve2_pkg;
CSR_MHPMCOUNTER10H = 12'hB8A,
CSR_MHPMCOUNTER11H = 12'hB8B,
CSR_MHPMCOUNTER12H = 12'hB8C,
CSR_MHPMCOUNTER13H = 12'hB8D,
CSR_MHPMCOUNTER14H = 12'hB8E,
CSR_MHPMCOUNTER15H = 12'hB8F,
CSR_MHPMCOUNTER16H = 12'hB90,
CSR_MHPMCOUNTER17H = 12'hB91,
CSR_MHPMCOUNTER18H = 12'hB92,
CSR_MHPMCOUNTER19H = 12'hB93,
CSR_MHPMCOUNTER20H = 12'hB94,
CSR_MHPMCOUNTER21H = 12'hB95,
CSR_MHPMCOUNTER22H = 12'hB96,
CSR_MHPMCOUNTER23H = 12'hB97,
CSR_MHPMCOUNTER24H = 12'hB98,
CSR_MHPMCOUNTER25H = 12'hB99,
CSR_MHPMCOUNTER26H = 12'hB9A,
CSR_MHPMCOUNTER27H = 12'hB9B,
CSR_MHPMCOUNTER28H = 12'hB9C,
CSR_MHPMCOUNTER29H = 12'hB9D,
CSR_MHPMCOUNTER30H = 12'hB9E,
CSR_MHPMCOUNTER31H = 12'hB9F,
CSR_CPUCTRL = 12'h7C0,
CSR_SECURESEED = 12'h7C1
} csr_num_e;
Expand Down