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@ikarostsin ikarostsin commented Dec 18, 2025

Based on the implementation of RiscvFlushIcache::flush, the second parameter should be the end address rather than the size of the memory region.

void RiscvFlushIcache::flush(uintptr_t start, uintptr_t end) {
  long ret = sys_flush_icache(start, end, SYS_RISCV_FLUSH_ICACHE_ALL);
  guarantee_with_errno(ret == 0, "riscv_flush_icache failed");

So this commit corrects the erroneous parameter passed to RiscvFlushIcache::flush in the icache_flush function call.


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  • JDK-8374056: RISC-V: Fix argument passing for the RiscvFlushIcache::flush (Bug - P4)

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This seems related to https://bugs.openjdk.org/browse/JDK-8310656.

Before JDK-8310656, we used to do a __builtin___clear_cache(addr, addr + (lines << ICache::log2_line_size));.

@robehn : Could you please confirm that?

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LGTM.


RiscvFlushIcache::flush((uintptr_t)addr, ((uintptr_t)lines) << ICache::log2_line_size);
uintptr_t end = (uintptr_t)addr + ((uintptr_t)lines << ICache::log2_line_size);
RiscvFlushIcache::flush((uintptr_t)addr, end);
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@RealFYang RealFYang Dec 19, 2025

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I checked latest kernel code (6.6 - 6.18), the syscall doesn't currently do anything with the address range.
I think that's why this doesn't affect functionality. But this needs to be fixed to avoid possible confusion.
(Created new JBS: https://bugs.openjdk.org/browse/JDK-8374056)

/*
 * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
 * having a direct 'fence.i' instruction available to userspace (which we
 * can't trap!), that's not actually viable when running on Linux because the
 * kernel might schedule a process on another hart.  There is no way for
 * userspace to handle this without invoking the kernel (as it doesn't know the
 * thread->hart mappings), so we've defined a RISC-V specific system call to
 * flush the instruction cache.
 *
 * sys_riscv_flush_icache() is defined to flush the instruction cache over an
 * address range, with the flush applying to either all threads or just the
 * caller.  We don't currently do anything with the address range, that's just
 * in there for forwards compatibility.
 */
SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end,
        uintptr_t, flags)
{
        /* Check the reserved flags. */
        if (unlikely(flags & ~SYS_RISCV_FLUSH_ICACHE_ALL))
                return -EINVAL;

        flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL);

        return 0;
}

@ikarostsin ikarostsin changed the title RISC-V: Fix argument passing for the RiscvFlushIcache::flush 8374056: RISC-V: Fix argument passing for the RiscvFlushIcache::flush Dec 19, 2025
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robehn commented Dec 19, 2025

Yes, so it looks like I got careless with the argument as I did know they did not matter...

My confusion came from:

Glibc usual one:
extern int cacheflush (void *__addr, const int __nbytes, const int __op)

Risc-V:
extern int __riscv_flush_icache (void *__start, void *__end, unsigned long int __flags);
SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end, uintptr_t, flags)

Thanks for fixing !

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