Fix data trapping in SDRAM

software/fpga/ov3/Makefile

@@ -15,7 +15,7 @@ $(FWPKG): $(BITFILE)
 	$(PYTHON) -m zipfile -c $@ $< $(BUILD)/map.txt
 
 $(BITFILE): $(PY_FILES)
-	$(PYTHON) build.py build_dir $(BUILD) build_name ov3
+	$(PYTHON) build.py $(BUILD) ov3
 
 clean:
 	rm -rf $(BUILD)/*

software/fpga/ov3/build.py

@@ -21,11 +21,13 @@ def gen_mapfile(ov3_mod):
     return r
 
 if __name__ == "__main__":
+    import sys
+
     plat = Platform()
     top = OV3(plat)
 
-    # Build the register map
-    # FIXME: build dir should come from command line arg
-    open("build/map.txt", "w").write(gen_mapfile(top))
+    _, build_dir, build_name = sys.argv
+
+    open("{}/map.txt".format(build_dir), "w").write(gen_mapfile(top))
 
-    plat.build(top)
+    plat.build(top, build_dir=build_dir, build_name=build_name)

software/fpga/ov3/ovhw/sdram_host_read.py

@@ -1,4 +1,5 @@
 from migen import *
+from migen.fhdl.decorators import ResetInserter
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.fifo import SyncFIFO
 from misoc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus
@@ -79,7 +80,7 @@ def __init__(self, hostif, host_burst_length = 16):
 
         self.submodules.sdram_read_fsm = FSM()
 
-        sdram_fifo = SyncFIFO(width, host_burst_length)
+        sdram_fifo = ResetInserter()(SyncFIFO(width, host_burst_length))
         self.submodules += sdram_fifo
 
         # we always read (never write)
@@ -137,6 +138,8 @@ def __init__(self, hostif, host_burst_length = 16):
         rptr_next = Signal(awidth)
         self.comb += If(wrap, rptr_next.eq(self._ring_base.storage)).Else(rptr_next.eq(self.rptr + 1))
 
+        self.sync += sdram_fifo.reset.eq(go &~ gor)
+
         self.sync += \
             If(go &~ gor, 
                 rptr.eq(self._ring_base.storage),

software/fpga/ov3/ovhw/sdram_sink.py

@@ -1,4 +1,5 @@
 from migen import *
+from migen.fhdl.decorators import ResetInserter
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.fifo import SyncFIFO
 from misoc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
@@ -16,7 +17,7 @@ def __init__(self, hostif, max_burst_length = 256):
 
         self.sink = Endpoint([('d', 8), ('last', 1)])
 
-        self.submodules.sdram_fifo = SyncFIFO(width, max_burst_length)
+        self.submodules.sdram_fifo = ResetInserter()(SyncFIFO(width, max_burst_length))
 
         self.submodules.fifo_write_fsm = FSM()
 
@@ -138,6 +139,8 @@ def __init__(self, hostif, max_burst_length = 256):
         # wrap around counter
         self.comb += If(wrap & hostif.d_stb &~ hostif.d_term, self._wrap_count.inc())
 
+        self.sync += self.sdram_fifo.reset.eq(go &~ gor)
+
         # update wptr
         self.sync += If(go &~ gor,
                 self.wptr.eq(self._ring_base.storage),
@@ -147,7 +150,9 @@ def __init__(self, hostif, max_burst_length = 256):
 
         # sink into fifo
 
-        self.submodules.fifo_fsm = FSM()
+        self.submodules.fifo_fsm = ResetInserter()(FSM())
+
+        self.sync += self.fifo_fsm.reset.eq(go &~ gor)
 
         capture_low = Signal()
         din_low = Signal(8)