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    • aihw-design-logs

      Public template
      Python
      1110Updated Oct 16, 2025Oct 16, 2025
    • Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.
      SystemVerilog
      21600Updated Oct 15, 2025Oct 15, 2025
    • SystemVerilog
      910233Updated Oct 15, 2025Oct 15, 2025
    • usb-host

      Public
      Repository for the USB Host project
      Makefile
      0000Updated Oct 13, 2025Oct 13, 2025
    • SystemVerilog
      2300Updated Oct 12, 2025Oct 12, 2025
    • This repository is the design log repo for GPU
      0000Updated Oct 11, 2025Oct 11, 2025
    • A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python
      Python
      41140Updated Oct 9, 2025Oct 9, 2025
    • OS-dev

      Public
      C
      0000Updated Oct 9, 2025Oct 9, 2025
    • FreeRTOS

      Public
      'Classic' FreeRTOS distribution. Started as Git clone of FreeRTOS SourceForge SVN repo. Submodules the kernel.
      C
      1.9k000Updated Oct 8, 2025Oct 8, 2025
    • RISC-V-CI

      Public
      Github actions for Continuous integration for RISC-V
      Shell
      0000Updated Sep 30, 2025Sep 30, 2025
    • amp-llvm

      Public
      The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
      LLVM
      15k000Updated Sep 5, 2025Sep 5, 2025
    • A lab designed to teach users how to write Verilator C++ testbenches
      C++
      0000Updated Sep 4, 2025Sep 4, 2025
    • 0000Updated Sep 4, 2025Sep 4, 2025
    • FPU

      Public
      Floating-point unit for RISC-V core
      SystemVerilog
      1300Updated Aug 8, 2025Aug 8, 2025
    • GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.
      C++
      580000Updated Aug 2, 2025Aug 2, 2025
    • Scala
      0000Updated Jul 30, 2025Jul 30, 2025
    • This is the PCB for PCB onboarding of SoCET using KiCAD 9.0.
      0000Updated Jul 3, 2025Jul 3, 2025
    • SoCET-CI

      Public
      GitHub Action for Continuous Integration of SoC with FuseSoC
      Shell
      0000Updated Jun 2, 2025Jun 2, 2025
    • SystemVerilog
      0300Updated May 10, 2025May 10, 2025
    • xv6-rv32

      Public
      Port of MIT's xv6 OS to 32 bit RISC V
      C
      19000Updated May 10, 2025May 10, 2025
    • SystemVerilog
      0000Updated May 4, 2025May 4, 2025
    • AXI-UVM

      Public
      SystemVerilog
      0100Updated May 4, 2025May 4, 2025
    • Minimal bare-metal RISC-V assembly code with UART output for execution in QEMU
      Assembly
      9000Updated May 4, 2025May 4, 2025
    • Python
      0000Updated May 4, 2025May 4, 2025
    • Public files for ZS project, everyone in socet have access to this repo
      SourcePawn
      0100Updated May 1, 2025May 1, 2025
    • fatfs-aft

      Public
      FatFs - Generic FAT File System Module
      C
      110000Updated Apr 29, 2025Apr 29, 2025
    • C++
      0100Updated Apr 24, 2025Apr 24, 2025
    • The main Embench repository
      C
      125000Updated Apr 24, 2025Apr 24, 2025
    • This is the previous full Synopsy Flow for test engineering members to reference
      Tcl
      0000Updated Apr 22, 2025Apr 22, 2025
    • vortexS25

      Public
      Verilog
      371000Updated Apr 22, 2025Apr 22, 2025