CHIPS Alliance

All

112 repositories

caliptra-sw
Public
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
Rust
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Apache License 2.0
•68•127•193•74•Updated Oct 15, 2025Oct 15, 2025
caliptra-ss
Public
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
security rot ocp root-of-trust caliptra opencomputeproject
SystemVerilog
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Apache License 2.0
•30•31•53•8•Updated Oct 15, 2025Oct 15, 2025
chisel
Public
Chisel: A Modern Hardware Design Language
scala chip-generator chisel rtl chisel3 firrtl verilog
Scala
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Apache License 2.0
•642•4.4k•341•144•Updated Oct 15, 2025Oct 15, 2025
verilator
Public
Verilator open-source SystemVerilog simulator and lint system
C++
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GNU Lesser General Public License v3.0
•709•41•0•0•Updated Oct 15, 2025Oct 15, 2025
t1
Public
Scala
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Apache License 2.0
•40•290•18•25•Updated Oct 15, 2025Oct 15, 2025
i3c-core
Public
SystemVerilog
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Apache License 2.0
•12•36•14•0•Updated Oct 15, 2025Oct 15, 2025
sv-tests
Public
Test suite designed to check compliance with the SystemVerilog standard.
rtl verilog systemverilog hdl compliance-testing symbiflow
SystemVerilog
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ISC License
•84•344•47•24•Updated Oct 15, 2025Oct 15, 2025
caliptra-ureg
Public
Rust
•
Apache License 2.0
•6•7•0•1•Updated Oct 14, 2025Oct 14, 2025
caliptra-rtl
Public
HW Design Collateral for Caliptra RoT IP
SystemVerilog
•
Apache License 2.0
•63•112•82•17•Updated Oct 13, 2025Oct 13, 2025
caliptra-mcu-sw
Public
Caliptra MCU Software
Rust
•
Apache License 2.0
•23•21•54•17•Updated Oct 11, 2025Oct 11, 2025
chips-alliance-website
Public
SCSS
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MIT License
•7•4•8•8•Updated Oct 11, 2025Oct 11, 2025
Caliptra
Public
Caliptra IP and firmware for integrated Root of Trust block
Apache License 2.0
•52•339•58•6•Updated Oct 11, 2025Oct 11, 2025
Cores-VeeR-EL2
Public
VeeR EL2 Core
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital
SystemVerilog
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Apache License 2.0
•89•298•31•3•Updated Oct 9, 2025Oct 9, 2025
tac
Public
CHIPS Alliance Technical Advisory Council
Apache License 2.0
•26•7•18•3•Updated Oct 8, 2025Oct 8, 2025
adams-bridge
Public
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
cryptography digital-signature lattice pqc ml-dsa-87
SystemVerilog
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Apache License 2.0
•7•35•20•0•Updated Oct 8, 2025Oct 8, 2025
firrtl-spec
Public
The specification for the FIRRTL language
TeX
•31•61•25•17•Updated Oct 4, 2025Oct 4, 2025
riscv-dv
Public
Random instruction generator for RISC-V processor verification
Python
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Apache License 2.0
•355•1.2k•129•20•Updated Oct 1, 2025Oct 1, 2025
sv-tests-results
Public
Output of the sv-tests runs.
HTML
•6•7•0•0•Updated Sep 29, 2025Sep 29, 2025
riscv-vector-tests
Public
Unit tests generator for RVV 1.0
generator spike riscv testsuite rvv
Go
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Apache License 2.0
•31•92•10•1•Updated Sep 25, 2025Sep 25, 2025
caliptra-dpe
Public
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
Rust
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Apache License 2.0
•26•18•19•8•Updated Sep 24, 2025Sep 24, 2025
caliptra-web
Public
Astro
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Apache License 2.0
•0•0•0•0•Updated Sep 24, 2025Sep 24, 2025
chisel-template
Public template
A template project for beginning new Chisel work
Shell
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The Unlicense
•194•663•12•2•Updated Sep 22, 2025Sep 22, 2025
verible-actions-common
Public
Apache License 2.0
•8•2•0•0•Updated Sep 17, 2025Sep 17, 2025
caliptra-infra
Public
Various tools used for Caliptra's Continuous Integration flows
Rust
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Apache License 2.0
•1•0•0•1•Updated Sep 16, 2025Sep 16, 2025
.github
Public
Organization profile for CHIPS Alliance
2•0•2•0•Updated Sep 16, 2025Sep 16, 2025
Surelog
Public
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
parser linter preprocessor antlr verilog python-api systemverilog uvm elaboration vpi
C++
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Apache License 2.0
•77•422•47•0•Updated Sep 6, 2025Sep 6, 2025
UHDM
Public
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
serialization listener systemverilog ieee-standard vpi-api vpi-interface
C++
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Apache License 2.0
•43•233•14•0•Updated Sep 6, 2025Sep 6, 2025
rocket-chip
Public
Rocket Chip Generator
scala rocket-chip chip-generator chisel riscv rtl
Scala
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Other
•1.2k•3.6k•250•67•Updated Sep 2, 2025Sep 2, 2025
rvdecoderdb
Public
The Scala parser to parse riscv/riscv-opcodes generate
Nix
•10•21•1•1•Updated Sep 2, 2025Sep 2, 2025
verible
Public
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
productivity parser formatter analysis style-linter linter language-server-protocol syntax-tree lexer yacc
C++
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Other
•256•1.7k•540•27•Updated Aug 29, 2025Aug 29, 2025