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    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      8274346Updated Oct 15, 2025Oct 15, 2025
    • u-boot

      Public
      Unofficial development fork of U-Boot
      C
      15110Updated Oct 15, 2025Oct 15, 2025
    • cva6

      Public
      The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
      Assembly
      8382.6k21510Updated Oct 14, 2025Oct 14, 2025
    • The purpose of the repo is to support CORE-V Wally architectural verification
      SystemVerilog
      3814362Updated Oct 13, 2025Oct 13, 2025
    • cvw

      Public
      CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
      SystemVerilog
      310424315Updated Oct 13, 2025Oct 13, 2025
    • Unified Access Page for the TRISTAN project
      HTML
      421933Updated Oct 9, 2025Oct 9, 2025
    • This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
      SystemVerilog
      661867612Updated Oct 2, 2025Oct 2, 2025
    • cve2

      Public
      The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
      SystemVerilog
      6524815110Updated Oct 1, 2025Oct 1, 2025
    • cvfpu-uvm

      Public
      UVM Verification Environment for the CVFPU
      Perl
      2510Updated Sep 29, 2025Sep 29, 2025
    • Functional verification project for the CORE-V family of RISC-V cores.
      Assembly
      25960213018Updated Sep 24, 2025Sep 24, 2025
    • OpenHW Group is a global, not-for-profit organization where hardware and software designers collaborate on open-source cores, IP, tools, and software. It provides infrastructure to host high-quality open-source hardware projects aligned with industry best practices.
      HTML
      111964Updated Sep 15, 2025Sep 15, 2025
    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      1415314114Updated Sep 1, 2025Sep 1, 2025
    • RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
      SystemVerilog
      379241Updated Aug 22, 2025Aug 22, 2025
    • Assembly
      9121Updated Aug 14, 2025Aug 14, 2025
    • cva5

      Public
      The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
      SystemVerilog
      2812140Updated Jul 11, 2025Jul 11, 2025
    • cv32e40p

      Public
      CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
      SystemVerilog
      4771.1k5211Updated May 26, 2025May 26, 2025
    • programs

      Public
      Documentation for the OpenHW Group's set of CORE-V RISC-V cores
      HTML
      99219910Updated May 22, 2025May 22, 2025
    • The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.
      HTML
      6100Updated Apr 22, 2025Apr 22, 2025
    • core-v-sw

      Public
      Main Repo for the OpenHW Group Software Task Group
      281760Updated Mar 11, 2025Mar 11, 2025
    • cv-mesh

      Public
      Verilog
      0400Updated Mar 10, 2025Mar 10, 2025
    • CORE-V Family of RISC-V Cores
      2230211Updated Feb 13, 2025Feb 13, 2025
    • Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
      SystemVerilog
      61800Updated Feb 12, 2025Feb 12, 2025
    • CV32E40S Design-Verification environment
      Assembly
      1010Updated Nov 11, 2024Nov 11, 2024
    • cv32e40x

      Public
      4 stage, in-order, compute RISC-V core based on the CV32E40P
      SystemVerilog
      52244315Updated Nov 6, 2024Nov 6, 2024
    • cv32e40s

      Public
      4 stage, in-order, secure RISC-V core based on the CV32E40P
      SystemVerilog
      2715032Updated Oct 31, 2024Oct 31, 2024
    • Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
      C
      6.3k102Updated Aug 16, 2024Aug 16, 2024
    • The OpenPiton Platform
      Assembly
      2511602Updated Aug 14, 2024Aug 14, 2024
    • C
      28940Updated Jul 30, 2024Jul 30, 2024
    • 181742Updated Jul 26, 2024Jul 26, 2024
    • CORE-V MCU UVM Environment and Test Bench
      SystemVerilog
      824160Updated Jul 19, 2024Jul 19, 2024