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    315 repositories

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •44•228•22•8•Updated Oct 14, 2025Oct 14, 2025

    • picobello

      Public
      whatever it means
      C
      •
      Other
      •7•11•7•3•Updated Oct 14, 2025Oct 14, 2025

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •79•289•15•20•Updated Oct 14, 2025Oct 14, 2025

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      Tcl
      •
      Other
      •26•10•1•3•Updated Oct 14, 2025Oct 14, 2025

    • ace

      Public
      SystemVerilog
      •
      Other
      •5•19•0•1•Updated Oct 13, 2025Oct 13, 2025

    • pulp-trainlib

      Public
      Floating-Point Optimized On-Device Learning Library for the PULP Platform.
      C
      •
      Apache License 2.0
      •18•37•4•2•Updated Oct 13, 2025Oct 13, 2025

    • Insitu-Cache

      Public
      SystemVerilog
      •
      Other
      •0•2•0•0•Updated Oct 12, 2025Oct 12, 2025

    • AraXL

      Public
      Assembly
      •
      Other
      •0•2•0•0•Updated Oct 10, 2025Oct 10, 2025

    • redmule

      Public
      SystemVerilog
      •
      Other
      •19•79•2•3•Updated Oct 10, 2025Oct 10, 2025

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •57•306•3•5•Updated Oct 9, 2025Oct 9, 2025

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •86•111•23•8•Updated Oct 9, 2025Oct 9, 2025

    • TeraNoC

      Public
      An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.
      C
      •
      Apache License 2.0
      •2•12•0•0•Updated Oct 9, 2025Oct 9, 2025

    • ManyRVData

      Public
      C
      •1•0•0•0•Updated Oct 9, 2025Oct 9, 2025

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      SystemVerilog
      •
      Apache License 2.0
      •4•10•1•1•Updated Oct 9, 2025Oct 9, 2025

    • cluster_interconnect

      Public
      SystemVerilog
      •
      Other
      •15•15•1•3•Updated Oct 9, 2025Oct 9, 2025

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •29•119•1•4•Updated Oct 8, 2025Oct 8, 2025

    • magia-sdk

      Public
      C
      •4•4•0•0•Updated Oct 7, 2025Oct 7, 2025

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •17•14•5•5•Updated Oct 7, 2025Oct 7, 2025

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •836•22•1•7•Updated Oct 7, 2025Oct 7, 2025

    • dram_rtl_sim

      Public
      SystemVerilog
      •
      Other
      •7•18•1•0•Updated Oct 7, 2025Oct 7, 2025

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •314•1.4k•48•17•Updated Oct 7, 2025Oct 7, 2025

    • apb

      Public
      APB Logic
      SystemVerilog
      •
      Other
      •16•20•2•5•Updated Oct 7, 2025Oct 7, 2025

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •53•325•25•10•Updated Oct 6, 2025Oct 6, 2025

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •73•144•2•5•Updated Oct 6, 2025Oct 6, 2025

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •21•52•9•9•Updated Oct 6, 2025Oct 6, 2025

    • wakelet

      Public
      Standalone, tiny, and low-power infrastructure to boost the HWPE flexiblity for always-on domains.
      Tcl
      •
      Apache License 2.0
      •0•2•0•0•Updated Oct 5, 2025Oct 5, 2025

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •32•108•5•2•Updated Oct 3, 2025Oct 3, 2025

    • hwpe-ctrl

      Public
      IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •20•6•2•4•Updated Oct 2, 2025Oct 2, 2025

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •38•49•7•5•Updated Sep 30, 2025Sep 30, 2025

    • regression_tests

      Public
      C
      •20•10•3•3•Updated Sep 30, 2025Sep 30, 2025