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@mp-17 mp-17 commented Oct 15, 2024

This is the second PR for Ara's FPGA and OS support. See #112 for the bare-metal one.

  • Add support for back-referencing FPGA flow (i.e., by driving the FPGA implementation from Ara's directory).
  • Adapt Ara-CVA6 interface to support virtual memory.
  • Bump Ara and CVA6.
  • Update the CI to test RVV Linux, Cheshire + Ara on VCU128, and its Linux boot.

Before merging, Ara and CVA6 should be referenced with TAGs laying on the main branch.

EDIT:
PR moved to #231, to integrate CVA6 version pulp-v2.

@mp-17 mp-17 force-pushed the mp/ara-pulpv1-os-rebase branch 7 times, most recently from 18cd941 to ce46d3c Compare October 16, 2024 16:36
@mp-17 mp-17 force-pushed the mp/ara-pulpv1-os-rebase branch 6 times, most recently from 6d4a76f to 858569a Compare October 19, 2024 10:39
@mp-17 mp-17 force-pushed the mp/ara-pulpv1-os-rebase branch from 858569a to dc2cbd1 Compare October 19, 2024 15:16
@mp-17 mp-17 requested a review from paulsc96 October 22, 2024 12:36
@mp-17 mp-17 self-assigned this Oct 22, 2024
@mp-17 mp-17 force-pushed the mp/ara-pulpv1 branch 2 times, most recently from 6170122 to dc79fa1 Compare October 22, 2024 16:50
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This is very clean as far as the diff in this repository.

The back-referencing setup however, while an intriguing construction, seems unnecessary. We can further discuss this offline, but:

  • To avoid the hardware back-reference (Bender script inject):
    • It is perfectly fine to unconditionally add Bender flags required by Ara to Cheshire; CVA6 does this too.
    • If you need these flags to be configurable (nr_lanes, vlen), it is best to introduce variables for them in the Cheshire make fragment (like those for the PLIC, CLINT etc.) and insert them in the build targets for the analyze scripts. This way, they can be overriden the same way as all other non-SV IP parameters.
    • If I missed something and you need to dynamically generate RTL (I don't think so), it would be great if you could follow the established method of creating an includable Make fragment in Ara to reconfigure its RTL from Cheshire as needed.
  • For the device tree, each (FPGA) target may have multiple device trees; you can simply add one called cheshire.vcu128_ara.dts using riscv,isa = "rv64imafdcv" instead of patching cheshire.dtsi.
  • For Linux, I don't necessarily mind if an Ara-ready image cannot (yet) be built directly from Cheshire. How we build and manage Linux is about to fundamentally change anyways, so adding a back-reference for this now is perhaps untimely. We can address this in a cleaner way in a later PR.

`endif
`ifdef ARA
ret.Ara = 1;
ret.AraVLEN = `ifdef VLEN `VLEN `else 0 `endif;
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Having these as defines is fine, but perhaps they should be prefixed to clarify they affect Ara

@mp-17 mp-17 closed this Jun 24, 2025
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mp-17 commented Jun 24, 2025

PR moved to #231, to integrate CVA6 version pulp-v2.

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3 participants