treewide: Optimizations for faster Verilator simulation #259
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This enables Verilator optimizations as it now understands there are no combinatorial loops. For the Cheshire SoC, this can reduce simulation time by around 3%.
This enables Verilator optimizations as it now understands there are no combinatorial loops. For the Cheshire SoC, this can reduce simulation time by around 2.5%.
In case the vector is not flipped, using a direct assignment can lead to an approximately 2% decrease in total system simulation time (measured using the Cheshire SoC).
This decreases total simulation time of the Cheshire SoC by around 1.8%.
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Everything looks good. The cb_filter is equivalent in all legal cases. Note: I think the lzc implementation should be optimized further but this is not part of this PR. |
Scheremo
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Sep 12, 2025
…m#259) * rr_arb_tree: Add Verilator pragmas to split tree node signals This enables Verilator optimizations as it now understands there are no combinatorial loops. For the Cheshire SoC, this can reduce simulation time by around 3%. * lzc: Add Verilator pragmas to split tree node signals This enables Verilator optimizations as it now understands there are no combinatorial loops. For the Cheshire SoC, this can reduce simulation time by around 2.5%. * lzc: Optimize reversing of input vector for Verilator speedup In case the vector is not flipped, using a direct assignment can lead to an approximately 2% decrease in total system simulation time (measured using the Cheshire SoC). * cb_filter: Logic simplification for Verilator speed-up This decreases total simulation time of the Cheshire SoC by around 1.8%.
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These modification are intended to generate better code for Verilator simulation without changing functional behavior.
Using the Cheshire SoC (pulp-platform/cheshire#230), these changes reduce total simulation time by around 8%.