Project Build and Simulation Guide

This readme provides instructions on how to set up and run the standalone simulation using make commands.

On the parametrization

Configure the hardware and testbench parameters in config.mk.

Hardware parameter

BANDWIDTH = total bandwidth of the HWPE towards TCDM, expressed in bits NUM_ELEM_WORD = number of elements (e.g., bytes) in a single word of a memory bank ELEM_WIDTH = width of an element, expressed in bits (e.g., 8 for bytes)

Constraints

• NUM_ELEM_WORD * ELEM_WIDTH is the width of a memory bank word. BANDWIDTH must be divisible by such word width, as BANDWIDTH / (NUM_ELEM_WORD * ELEM_WIDTH) is the number of banks accessed in parallel by the HWPE in one memory access.
• NUM_ELEM_WORD must be a power of two due to memory addressing. Currently, the configurations NUM_ELEM_WORD = 2,4 support the datamover's transposition mode (1 elem, 2 elems, 4 elems). NUM_ELEM_WORD = 1 and NUM_ELEM_WORD > 4 is not supported.

Testbench parameters

The following parameters are used to generate the testbench stimuli and to configure the datamover registers.

STIM_*_BASE_ADDR = start address of the read/write access bursts (element-addressed) STIM_*_LENGTH = number of read/write accesses for the d0/d1 dimensions and in total (it is not an address offset!) STIM_*_STRIDE = stride between element across dimensions d0/d1 (element-addressed, e.g., stride d1 would be the distance in an element-addressed offset between A[row=0][col=0] and A[row=1][col=0]) STIM_MEM_SIZE = number of words of the testbench memory STIM_TRANSP_MODE = transposition mode to configure for the datamover (3'b000 = none, 3'b001 = 1 elem, 3'b010 = 2 elem, 3'b100 = 4 elem)

For the complete list of the datamover configuration registers, cf. datamover_package.sv.

The parameters STIM_*_BASE_ADDR and STIM_*_STRIDE, exactly like memory addresses, are element-addressed. In a classical configuration of NUM_ELEM_WORD and ELEM_WIDTH (i.e., 32-bit words made of 4 8-bit bytes each), they are byte-addressed and their least significant 2 bits are dedicated to the byte offset. In general, however, the least $clog2(NUM_ELEM_WORD) bits of these addresses are dedicated to the offset for the elements in a word. This impacts the generation of the stimuli in verif/python/generate_stimuli.py and the memory addressing in the hardware (i.e., the testbench_memory employed in this simulation or the memory sub-system of a real system where the datamover is integrated).

Note: STIM_*_D0_STRIDE is a element-addressed offset. This means that subsequent accesses advance of STIM_*_D0_STRIDE << $clog2(NUM_ELEM_WORD) in memory, independently on BANDWIDTH. BANDWIDTH only indicates the accessed number of subsequent words, given the base word of that access. Therefore, depending on the configuration of the stride, subsequent accesses of BANDWIDTH bits can also access overlapping words.

Constraints

• Currently, only STIM_TRANSP_MODE = 000 (i.e., no transposition) is supported by verif/python/generate_stimuli.py; it is not possible, therefore, to test the transpose functionality of the datamover in this standalone testbench

Available Make Commands

1. To clone the dependencies, run:

make bender

2. Generate Stimuli and Golden Files

To generate the stimuli and golden reference using a Python script, run:

make stimuli

3. Create Compilation Script

To create a compilation script for compiling the hardware, run:

make sim-script

4. Simulate the Design

To simulate the RTL, execute:

make sim

By default QuestaSim GUI is active. You can simulate the RTL in CLI mode with GUI=0 make sim.

Test Results

If the tests pass successfully, you should see the following message displayed at the end:

PASSED!!!!

Contributors

• Francesco Conti, University of Bologna ([email protected])
• Arpan Suravi Prasad, ETH Zurich ([email protected])

License

This repository makes use of two licenses:

• for all software: Apache License Version 2.0
• for all hardware: Solderpad Hardware License Version 0.51

For further information have a look at the license files: LICENSE.hw, LICENSE.sw