Migrate hardware dependencies from Git submodules to Bender

.github/workflows/ci.yml

@@ -247,7 +247,7 @@ jobs:
       run: pip install -r python-requirements.txt
     - name: Build Control Registers
       run: |
-        git submodule update --init --recursive -- hardware/deps/register_interface
+        make bender
         git apply hardware/deps/patches/register_interface.patch
         make -C hardware/src/control_registers clean
         make -C hardware/src/control_registers all

.gitmodules

@@ -10,39 +10,9 @@
 [submodule "toolchain/verilator"]
 	path = toolchain/verilator
 	url = https://github.com/verilator/verilator.git
-[submodule "hardware/deps/axi"]
-	path = hardware/deps/axi
-	url = https://github.com/pulp-platform/axi.git
-[submodule "hardware/deps/cluster_interconnect"]
-	path = hardware/deps/cluster_interconnect
-	url = https://github.com/pulp-platform/cluster_interconnect.git
-[submodule "hardware/deps/common_cells"]
-	path = hardware/deps/common_cells
-	url = https://github.com/pulp-platform/common_cells.git
-[submodule "hardware/deps/common_verification"]
-	path = hardware/deps/common_verification
-	url = https://github.com/pulp-platform/common_verification.git
-[submodule "hardware/deps/register_interface"]
-	path = hardware/deps/register_interface
-	url = https://github.com/pulp-platform/register_interface.git
-[submodule "hardware/deps/tech_cells_generic"]
-	path = hardware/deps/tech_cells_generic
-	url = https://github.com/pulp-platform/tech_cells_generic.git
 [submodule "toolchain/riscv-opcodes"]
 	path = toolchain/riscv-opcodes
 	url = https://github.com/pulp-platform/riscv-opcodes.git
-[submodule "hardware/deps/apb"]
-	path = hardware/deps/apb
-	url = https://github.com/pulp-platform/apb.git
-[submodule "hardware/deps/fpnew"]
-	path = hardware/deps/fpnew
-	url = https://github.com/pulp-platform/cvfpu.git
-[submodule "hardware/deps/fpu_div_sqrt_mvp"]
-	path = hardware/deps/fpu_div_sqrt_mvp
-	url = https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
 [submodule "hardware/deps/dram_rtl_sim"]
 	path = hardware/deps/dram_rtl_sim
 	url = https://github.com/pulp-platform/dram_rtl_sim.git
-[submodule "hardware/deps/cluster_icache"]
-	path = hardware/deps/cluster_icache
-	url = https://github.com/pulp-platform/cluster_icache.git

Bender.lock

@@ -1,16 +1,16 @@
 packages:
   apb:
-    revision: null
-    version: null
+    revision: 77ddf073f194d44b9119949d2421be59789e69ae
+    version: 0.2.4
     source:
-      Path: hardware/deps/apb
+      Git: https://github.com/pulp-platform/apb.git
     dependencies:
     - common_cells
   axi:
-    revision: null
-    version: null
+    revision: ac5deb3ff086aa34b168f392c051e92603d6c0e2
+    version: 0.39.2
     source:
-      Path: hardware/deps/axi
+      Git: https://github.com/pulp-platform/axi.git
     dependencies:
     - common_cells
     - common_verification
@@ -26,39 +26,39 @@ packages:
     - scm
     - tech_cells_generic
   cluster_interconnect:
-    revision: null
-    version: null
+    revision: 7d0a4f8acae71a583a6713cab5554e60b9bb8d27
+    version: 1.2.1
     source:
-      Path: hardware/deps/cluster_interconnect
+      Git: https://github.com/pulp-platform/cluster_interconnect.git
     dependencies:
     - common_cells
   common_cells:
-    revision: null
-    version: null
+    revision: 13f28aa0021fc22c0d01a12d618fda58d2c93239
+    version: 1.33.0
     source:
-      Path: hardware/deps/common_cells
+      Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
     - common_verification
     - tech_cells_generic
   common_verification:
-    revision: null
-    version: null
+    revision: 9c07fa860593b2caabd9b5681740c25fac04b878
+    version: 0.2.3
     source:
-      Path: hardware/deps/common_verification
+      Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   fpnew:
-    revision: null
+    revision: 9481d57c161bb160fd294eae07279082bff06698
     version: null
     source:
-      Path: hardware/deps/fpnew
+      Git: https://github.com/pulp-platform/cvfpu.git
     dependencies:
     - common_cells
     - fpu_div_sqrt_mvp
   fpu_div_sqrt_mvp:
-    revision: null
+    revision: 917dd79cb2dc1a8f43df1a84e0e4231508a980e9
     version: null
     source:
-      Path: hardware/deps/fpu_div_sqrt_mvp
+      Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
     dependencies:
     - common_cells
   idma:
@@ -72,10 +72,10 @@ packages:
     - common_verification
     - register_interface
   register_interface:
-    revision: null
-    version: null
+    revision: e25b36670ff7aab3402f40efcc2b11ee0f31cf19
+    version: 0.4.3
     source:
-      Path: hardware/deps/register_interface
+      Git: https://github.com/pulp-platform/register_interface.git
     dependencies:
     - apb
     - axi
@@ -104,9 +104,9 @@ packages:
     - axi
     - common_cells
   tech_cells_generic:
-    revision: null
-    version: null
+    revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
+    version: 0.2.13
     source:
-      Path: hardware/deps/tech_cells_generic
+      Git: https://github.com/pulp-platform/tech_cells_generic.git
     dependencies:
     - common_verification

Makefile

@@ -21,6 +21,7 @@ ISA_SIM_INSTALL_DIR   ?= ${INSTALL_DIR}/riscv-isa-sim
 LLVM_INSTALL_DIR      ?= ${INSTALL_DIR}/llvm
 HALIDE_INSTALL_DIR    ?= ${INSTALL_DIR}/halide
 BENDER_INSTALL_DIR    ?= ${INSTALL_DIR}/bender
+BENDER                ?= ${BENDER_INSTALL_DIR}/bender
 VERILATOR_INSTALL_DIR ?= ${INSTALL_DIR}/verilator
 RISCV_TESTS_DIR       ?= ${ROOT_DIR}/${SOFTWARE_DIR}/riscv-tests
 
@@ -54,6 +55,35 @@ else
   CLANG_LDFLAGS  := ""
 endif
 
+# Update Bender dependencies
+BENDER_ROOT ?= $(ROOT_DIR)/hardware/deps
+
+# Ensure both Bender dependencies and (essential) submodules are checked out
+$(BENDER_ROOT)/.mempool_deps: $(BENDER_INSTALL_DIR)/bender
+	cd $(ROOT_DIR) && $(BENDER) checkout
+	@touch $@
+
+# Make sure dependencies are more up-to-date than any targets run
+ifeq ($(shell test -f $(BENDER_ROOT)/.mempool_deps && echo 1),)
+-include $(BENDER_ROOT)/.mempool_deps
+endif
+
+# Running this target will reset dependencies (without updating the checked-in Bender.lock)
+.PHONY: clean-deps
+clean-deps:
+	cd $(BENDER_ROOT) && rm -rf \
+		apb \
+		axi \
+		cluster_icache \
+		cluster_interconnect \
+		common_cells \
+		common_verification \
+		fpnew \
+		fpu_div_sqrt_mvp \
+		register_interface \
+		tech_cells_generic
+	rm -f $(BENDER_ROOT)/.mempool_deps
+
 # Default target
 all: toolchain riscv-isa-sim halide
 
@@ -152,7 +182,7 @@ $(VERILATOR_INSTALL_DIR)/bin/verilator: toolchain/verilator Makefile
 # Update and patch hardware dependencies for MemPool
 # Previous changes will be stashed. Clear all the stashes with `git stash clear`
 .PHONY: update-deps
-update-deps: setup-dram
+update-deps: setup-dram $(BENDER_ROOT)/.mempool_deps
 	for dep in $(shell git config --file .gitmodules --get-regexp path \
 	| awk '/hardware/{ print $$2 }'); do \
 	  git -C $${dep} diff --quiet || { echo $${dep}; git -C $${dep} stash -u; }; \

hardware/Makefile

@@ -166,6 +166,35 @@ cpp_defs += -DAXI_DATA_WIDTH=$(axi_data_width)
 
 .DEFAULT_GOAL := compile
 
+# Update Bender dependencies
+BENDER_ROOT ?= $(ROOT_DIR)/deps
+
+# Ensure both Bender dependencies and (essential) submodules are checked out
+$(BENDER_ROOT)/.mempool_deps: $(bender)
+	cd $(ROOT_DIR)/.. $(bender) checkout
+	@touch $@
+
+# Make sure dependencies are more up-to-date than any targets run
+ifeq ($(shell test -f $(BENDER_ROOT)/.mempool_deps && echo 1),)
+-include $(BENDER_ROOT)/.mempool_deps
+endif
+
+# Running this target will reset dependencies (without updating the checked-in Bender.lock)
+.PHONY: clean-deps
+clean-deps:
+	cd $(BENDER_ROOT) && rm -rf \
+		apb \
+		axi \
+		cluster_icache \
+		cluster_interconnect \
+		common_cells \
+		common_verification \
+		fpnew \
+		fpu_div_sqrt_mvp \
+		register_interface \
+		tech_cells_generic
+	rm -f $(BENDER_ROOT)/.mempool_deps
+
 # Build path
 $(buildpath):
 	mkdir -p $(buildpath)

hardware/deps/.gitignore

@@ -0,0 +1,11 @@
+apb/
+axi/
+cluster_icache/
+cluster_interconnect/
+common_cells/
+common_verification/
+fpnew/
+fpu_div_sqrt_mvp/
+register_interface/
+tech_cells_generic/
+.mempool_deps